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1. 发明申请

WO2005101190A2 PROCESSOR HAVING PARALLEL VECTOR MULTIPLY AND REDUCE OPERATIONS WITH SEQUENTIAL SEMANTICS 审中-公开
标题翻译：具有并行矢量多项式和减少运算顺序语义的处理器
公开(公告)号：WO2005101190A2
公开(公告)日：2005-10-27
申请号：PCT/US2005/011976
申请日：2005-04-07
申请人： SANDBRIDGE TECHNOLOGIES, INC. , HOKENEK, Erdem , SCHULTE, Michael, J. , MOUDGILL, Mayan , GLOSSNER, John, C.
发明人： HOKENEK, Erdem , SCHULTE, Michael, J. , MOUDGILL, Mayan , GLOSSNER, John, C.
IPC分类号： G06F7/00
CPC分类号： G06F9/3001 , G06F7/49921 , G06F7/5443 , G06F2207/3828 , G06F2207/388
摘要： A processor comprises a plurality of arithmetic units, an accumulator unit, and a reduction unit coupled between the plurality of arithmetic units and the accumulator unit. The reduction unit receives products of vector elements from the arithmetic units and a first accumulator value from the accumulator unit, and processes the products and the first accumulator value to generate a second accumulator value for delivery to the accumulator unit. The processor implements a plurality of vector multiply and reduce operations having guaranteed sequential semantics, that is, operations which guarantee that the computational result will be the same as that which would be produced using a corresponding sequence of individual instructions.
摘要翻译：处理器包括多个运算单元，累加器单元和耦合在所述多个运算单元和所述累加器单元之间的缩减单元。还原单元从算术单元接收向量元素的乘积和来自累加器单元的第一累加器值，并且处理乘积和第一累加器值以产生用于递送到累加器单元的第二累加器值。处理器实现多个向量乘法和减少具有保证的顺序语义的操作，即，确保计算结果将与使用单独指令的相应序列产生的计算结果相同的操作。

2. 发明申请

WO2005099383A2 PROCESSOR HAVING COMPOUND INSTRUCTION AND OPERATION FORMATS 审中-公开
标题翻译：具有化合物指导和操作格式的处理器
公开(公告)号：WO2005099383A2
公开(公告)日：2005-10-27
申请号：PCT/US2005/011613
申请日：2005-04-07
申请人： SANDBRIDGE TECHNOLOGIES, INC. , GLOSSNER, C. John , HOKENEK, Erdem , MOUDGILL, Mayan , SCHULTE, Michael, J.
发明人： GLOSSNER, C. John , HOKENEK, Erdem , MOUDGILL, Mayan , SCHULTE, Michael, J.
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/30036 , G06F9/30167 , G06F9/3853
摘要： A processor comprises a memory, an instruction decoder coupled to the memory for decoding instructions retrieved therefrom, and a plurality of execution units for executing the decoded instructions. One or more of the instructions are in a compound instruction format in which a single instruction comprises multiple operation fields, with one or more of the operation fields each comprising at least an operation code field and a function field. The operation code field and the function field together specify a particular operation to be performed by one or more of the execution units.
摘要翻译：处理器包括存储器，耦合到存储器的用于解码从其中检索的指令的指令解码器，以及用于执行解码指令的多个执行单元。一个或多个指令是复合指令格式，其中单个指令包括多个操作字段，其中一个或多个操作字段各自至少包括操作码字段和功能字段。操作代码字段和功能字段一起指定由一个或多个执行单元执行的特定操作。

3. 发明申请

WO2004103056A2 PROCESSOR REDUCTION UNIT FOR ACCUMULATION OF MULTIPLE OPERANDS WITH OR WITHOUT SATURATION 审中-公开
标题翻译：用于累积或不饱和的多个操作的处理器减少单元
公开(公告)号：WO2004103056A2
公开(公告)日：2004-12-02
申请号：PCT/US2004/014257
申请日：2004-05-07
申请人： SANDBRIDGE TECHNOLOGIES, INC.
发明人： SCHULTE, Michael, J. , BALZOLA, Pablo, I. , HOKENEK, Erdem , GLOSSNER, John, C.
IPC分类号： G06F7/00 , G06F7/38 , G06F7/544 , G06F9/302 , G06F9/38
CPC分类号： G06F9/30101 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/3851 , G06F9/3893
摘要： A processor having a reduction unit that sums m input operands plus an accumulator value, with the option of saturating after each addition or wrapping around the result of each addition. The reduction unit also allows the m input operands to be subtracted from the accumulator value by simply inverting the bits of the input operands and setting a carry into each of a plurality of reduction adders to one. The reduction unit can be used in conjunction with m parallel multipliers to quickly perform dot products and other vector operations with either saturating or wrap-around arithmetic.
摘要翻译：具有减少单元的处理器，其将m个输入操作数加上累加器值相加，并且可以在每次添加之后饱和选项或围绕每次添加的结果进行包围。缩小单元还允许通过简单地反转输入操作数的位并将多个还原加法器中的每一个设置为一个，从累加器值中减去m个输入操作数。还原单元可以与m个并行乘法器一起使用，以便通过饱和或环绕运算来快速执行点积和其他向量运算。

4. 发明申请

WO2006071385A2 DATA FILE STORING MULTIPLE DATA TYPES WITH CONTROLLED DATA ACCESS 审中-公开
标题翻译：数据文件存储具有受控数据访问的多种数据类型
公开(公告)号：WO2006071385A2
公开(公告)日：2006-07-06
申请号：PCT/US2005/041419
申请日：2005-11-15
申请人： SANDBRIDGE TECHNOLOGIES, INC. , HOKENEK, Erdem , MOUDGILL, Mayan , GLOSSNER, C.,John , SCHULTE, Michael, J.
发明人： HOKENEK, Erdem , MOUDGILL, Mayan , GLOSSNER, C.,John , SCHULTE, Michael, J.
IPC分类号： G06F15/00
CPC分类号： G06F9/30112
摘要： A method and apparatus for efficiently storing multiple data types in a computer’s register or data file. A single data file can store data with a variety of sizes and number formats, including integers, fractions, and mixed numbers. The register file is partitioned into fields, such that only the relevant portions of the register file are read or written.
摘要翻译：一种用于在计算机的寄存器或数据文件中有效地存储多种数据类型的方法和装置。单个数据文件可以存储具有各种大小和数字格式的数据，包括整数，分数和混合数。寄存器文件被分割成字段，使得仅读取或写入寄存器文件的相关部分。

5. 发明申请

WO2005101221A1 MULTITHREADED PROCESSOR WITH MULTIPLE CONCURRENT PIPELINES PER THREAD 审中-公开
标题翻译：多通道加工器，每个螺纹多个并流管道
公开(公告)号：WO2005101221A1
公开(公告)日：2005-10-27
申请号：PCT/US2005/011614
申请日：2005-04-07
申请人： SANDBRIDGE TECHNOLOGIES, INC. , HOKENEK, Erdem , MOUDGILL, Mayan , SCHULTE, Michael, J. , GLOSSNER, C., John
发明人： HOKENEK, Erdem , MOUDGILL, Mayan , SCHULTE, Michael, J. , GLOSSNER, C., John
IPC分类号： G06F15/00
CPC分类号： G06F9/3851 , G06F9/30036 , G06F9/30101 , G06F9/30123 , G06F9/3893
摘要： A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.
摘要翻译：多线程处理器包括多个硬件线程单元，耦合到用于解码从其接收的指令的线程单元的指令解码器，以及用于执行解码指令的多个执行单元。多线程处理器被配置为用于控制与相应硬件线程单元相关联的线程的指令发布序列。在给定的处理器时钟周期中，仅允许指定的一个线程发出一个或多个指令，但是允许发出指令的指定线程根据指令发布顺序在多个时钟周期内变化。这些指令以允许至少给定的一个线程支持多个并行指令流水线的方式流水线化。

6. 发明申请

WO2005010746A1 ARITHMETIC UNIT FOR ADDITION OR SUBTRACTION WITH PRELIMINARY SATURATION DETECTION 审中-公开
标题翻译：用于添加或减去初步饱和度检测的算术单元
公开(公告)号：WO2005010746A1
公开(公告)日：2005-02-03
申请号：PCT/US2004/023431
申请日：2004-07-21
申请人： SANDBRIDGE TECHNOLOGIES, INC. , SCHULTE, Michael, J. , HOKENEK, Erdem , BALZOLA, Pablo, I. , GLOSSNER, John, C.
发明人： SCHULTE, Michael, J. , HOKENEK, Erdem , BALZOLA, Pablo, I. , GLOSSNER, John, C.
IPC分类号： G06F7/50
CPC分类号： G06F7/507 , G06F7/49921
摘要： An arithmetic unit for performing an arithmetic operation on at least first and second input operands, each of the input operands being separable into a first portion and a second portion, such as respective less significant and more significant portions. The arithmetic unit comprises first arithmetic circuitry, second arithmetic circuitry, selection circuitry and saturation circuitry. The first arithmetic circuitry, which may comprise a carry-propagate adder, processes the first portions of the input operands to generate at least a temporary sum and a carry output. The second arithmetic circuitry, which may comprise a dual adder and a preliminary saturation detector, processes the second portions of the input operands to generate one or more temporary sums and a number of saturation flags. The selection circuitry is configured to select one or more of the outputs of the second arithmetic circuitry based on the carry output of the first arithmetic circuitry. The saturation circuitry has inputs coupled to corresponding outputs of the first arithmetic circuitry and the selection circuitry, and is configured to generate a result of the arithmetic operation.
摘要翻译：一种用于对至少第一和第二输入操作数执行算术运算的算术单元，每个输入操作数可分为第一部分和第二部分，例如各自不太重要和更重要的部分。算术单元包括第一运算电路，第二运算电路，选择电路和饱和电路。可以包括进位传播加法器的第一运算电路处理输入操作数的第一部分以产生至少一个临时和和进位输出。可以包括双加法器和初步饱和检测器的第二运算电路处理输入操作数的第二部分以产生一个或多个临时和和多个饱和标志。选择电路被配置为基于第一运算电路的进位输出来选择第二运算电路的一个或多个输出。饱和电路具有耦合到第一算术电路和选择电路的对应输出的输入，并且被配置为产生算术运算的结果。

7. 发明公开

EP1761860A2 PROCESSOR HAVING COMPOUND INSTRUCTION AND OPERATION FORMATS 审中-公开
标题翻译：与VERBUNDANWEISUNGS-和操作FORMATS处理器
公开(公告)号：EP1761860A2
公开(公告)日：2007-03-14
申请号：EP05732948.4
申请日：2005-04-07
申请人： Sandbridge Technologies, Inc.
发明人： GLOSSNER, C. John , HOKENEK, Erdem , MOUDGILL, Mayan , SCHULTE, Michael, J.
IPC分类号： G06F15/00
CPC分类号： G06F9/30145 , G06F9/30036 , G06F9/30167 , G06F9/3853
摘要： A processor (400) comprises a memory (412-1), an instruction decoder (416) coupled to the memory for decoding instructions retrieved therefrom, and a plurality of execution units (460) for executing the decoded instructions One or more of the instructions are in a compound instruction format in which a single instruction comprises multiple operation fields, with one or more of the operation fields each comprising at least an operation code field and a function field. The operation code field and the function field together specify a particular operation to be performed by one or more of the execution units.

8. 发明公开

EP1652063A1 ARITHMETIC UNIT FOR ADDITION OR SUBTRACTION WITH PRELIMINARY SATURATION DETECTION 审中-公开
标题翻译：运算单元进行加减有了初步饱和检测
公开(公告)号：EP1652063A1
公开(公告)日：2006-05-03
申请号：EP04778784.1
申请日：2004-07-21
申请人： Sandbridge Technologies, Inc.
发明人： SCHULTE, Michael, J. , HOKENEK, Erdem , BALZOLA, Pablo, I. , GLOSSNER, John, C.
IPC分类号： G06F7/50 , G06F7/38
CPC分类号： G06F7/507 , G06F7/49921
摘要： An arithmetic unit for performing an arithmetic operation on at least first and second input operands, each of the input operands being separable into a first portion and a second portion, such as respective less significant and more significant portions. The arithmetic unit comprises first arithmetic circuitry, second arithmetic circuitry, selection circuitry and saturation circuitry. The first arithmetic circuitry, which may comprise a carry-propagate adder, processes the first portions of the input operands to generate at least a temporary sum and a carry output. The second arithmetic circuitry, which may comprise a dual adder and a preliminary saturation detector, processes the second portions of the input operands to generate one or more temporary sums and a number of saturation flags. The selection circuitry is configured to select one or more of the outputs of the second arithmetic circuitry based on the carry output of the first arithmetic circuitry. The saturation circuitry has inputs coupled to corresponding outputs of the first arithmetic circuitry and the selection circuitry, and is configured to generate a result of the arithmetic operation.

9. 发明公开

EP1735694A2 PROCESSOR HAVING PARALLEL VECTOR MULTIPLY AND REDUCE OPERATIONS WITH SEQUENTIAL SEMANTICS 审中-公开
标题翻译：与顺序语义并行向量乘法和归约操作处理器
公开(公告)号：EP1735694A2
公开(公告)日：2006-12-27
申请号：EP05734929.2
申请日：2005-04-07
申请人： Sandbridge Technologies, Inc.
发明人： HOKENEK, Erdem , SCHULTE, Michael, J. , MOUDGILL, Mayan , GLOSSNER, John, C.
IPC分类号： G06F7/00
CPC分类号： G06F9/3001 , G06F7/49921 , G06F7/5443 , G06F2207/3828 , G06F2207/388
摘要： A processor comprises a plurality of arithmetic units, an accumulator unit, and a reduction unit coupled between the plurality of arithmetic units and the accumulator unit. The reduction unit receives products of vector elements from the arithmetic units and a first accumulator value from the accumulator unit, and processes the products and the first accumulator value to generate a second accumulator value for delivery to the accumulator unit. The processor implements a plurality of vector multiply and reduce operations having guaranteed sequential semantics, that is, operations which guarantee that the computational result will be the same as that which would be produced using a corresponding sequence of individual instructions.

10. 发明公开

EP1623307A2 PROCESSOR REDUCTION UNIT FOR ACCUMULATION OF MULTIPLE OPERANDS WITH OR WITHOUT SATURATION 有权转让
标题翻译：处理器减速装置积累以有或无饱和多个操作数
公开(公告)号：EP1623307A2
公开(公告)日：2006-02-08
申请号：EP04775953.5
申请日：2004-05-07
申请人： Sandbridge Technologies, Inc.
发明人： SCHULTE, Michael, J. , BALZOLA, Pablo, I. , HOKENEK, Erdem , GLOSSNER, John, C.
IPC分类号： G06F1/00
CPC分类号： G06F9/30101 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/3851 , G06F9/3893
摘要： A processor having a reduction unit that sums m input operands plus an accumulator value, with the option of saturating after each addition or wrapping around the result of each addition. The reduction unit also allows the m input operands to be subtracted from the accumulator value by simply inverting the bits of the input operands and setting a carry into each of a plurality of reduction adders to one. The reduction unit can be used in conjunction with m parallel multipliers to quickly perform dot products and other vector operations with either saturating or wrap-around arithmetic.

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