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1. 发明申请

WO2005099383A2 PROCESSOR HAVING COMPOUND INSTRUCTION AND OPERATION FORMATS 审中-公开
标题翻译：具有化合物指导和操作格式的处理器
公开(公告)号：WO2005099383A2
公开(公告)日：2005-10-27
申请号：PCT/US2005/011613
申请日：2005-04-07
申请人： SANDBRIDGE TECHNOLOGIES, INC. , GLOSSNER, C. John , HOKENEK, Erdem , MOUDGILL, Mayan , SCHULTE, Michael, J.
发明人： GLOSSNER, C. John , HOKENEK, Erdem , MOUDGILL, Mayan , SCHULTE, Michael, J.
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/30036 , G06F9/30167 , G06F9/3853
摘要： A processor comprises a memory, an instruction decoder coupled to the memory for decoding instructions retrieved therefrom, and a plurality of execution units for executing the decoded instructions. One or more of the instructions are in a compound instruction format in which a single instruction comprises multiple operation fields, with one or more of the operation fields each comprising at least an operation code field and a function field. The operation code field and the function field together specify a particular operation to be performed by one or more of the execution units.
摘要翻译：处理器包括存储器，耦合到存储器的用于解码从其中检索的指令的指令解码器，以及用于执行解码指令的多个执行单元。一个或多个指令是复合指令格式，其中单个指令包括多个操作字段，其中一个或多个操作字段各自至少包括操作码字段和功能字段。操作代码字段和功能字段一起指定由一个或多个执行单元执行的特定操作。

2. 发明申请

WO2004103056A2 PROCESSOR REDUCTION UNIT FOR ACCUMULATION OF MULTIPLE OPERANDS WITH OR WITHOUT SATURATION 审中-公开
标题翻译：用于累积或不饱和的多个操作的处理器减少单元
公开(公告)号：WO2004103056A2
公开(公告)日：2004-12-02
申请号：PCT/US2004/014257
申请日：2004-05-07
申请人： SANDBRIDGE TECHNOLOGIES, INC.
发明人： SCHULTE, Michael, J. , BALZOLA, Pablo, I. , HOKENEK, Erdem , GLOSSNER, John, C.
IPC分类号： G06F7/00 , G06F7/38 , G06F7/544 , G06F9/302 , G06F9/38
CPC分类号： G06F9/30101 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/3851 , G06F9/3893
摘要： A processor having a reduction unit that sums m input operands plus an accumulator value, with the option of saturating after each addition or wrapping around the result of each addition. The reduction unit also allows the m input operands to be subtracted from the accumulator value by simply inverting the bits of the input operands and setting a carry into each of a plurality of reduction adders to one. The reduction unit can be used in conjunction with m parallel multipliers to quickly perform dot products and other vector operations with either saturating or wrap-around arithmetic.
摘要翻译：具有减少单元的处理器，其将m个输入操作数加上累加器值相加，并且可以在每次添加之后饱和选项或围绕每次添加的结果进行包围。缩小单元还允许通过简单地反转输入操作数的位并将多个还原加法器中的每一个设置为一个，从累加器值中减去m个输入操作数。还原单元可以与m个并行乘法器一起使用，以便通过饱和或环绕运算来快速执行点积和其他向量运算。

3. 发明申请

WO2004034209A3 METHOD AND APPARATUS FOR REGISTER FILE PORT REDUCTION IN A MULTITHREADED PROCESSOR 审中-公开
公开(公告)号：WO2004034209A3
公开(公告)日：2004-04-22
申请号：PCT/US2003/031904
申请日：2003-10-09
申请人： SANDBRIDGE TECHNOLOGIES, INC.
发明人： HOKENEK, Erdem , MOUDGILL, Mayan , GLOSSNER, C., John
IPC分类号： G06F9/00
摘要： Techniques for thread-based register file access by a multithreaded processor are disclosed. The multithreaded processor determines a thread identifier associated with a particular processor thread, and utilizes at least a portion of the thread identifier to select a particular portion of an associated register file to be accessed by the corresponding processor thread. In an illustrative embodiment, the register file is divided into even and odd portions, with a least significant bit or other portion of the thread identifier being used to select either the even or the odd portion for use by a given processor thread. The thread-based register file selection may be utilized in conjunction with token triggered threading and instruction pipelining. Advantageously, the invention reduces register file port requirements and thus processor power consumption, while maintaining desired levels of concurrency.

4. 发明申请

WO2005008274A1 DOPPLER COMPENSATED RECEIVER 审中-公开
标题翻译：多普勒补偿接收器
公开(公告)号：WO2005008274A1
公开(公告)日：2005-01-27
申请号：PCT/US2004/021656
申请日：2004-07-07
申请人： SANDBRIDGE TECHNOLOGIES, INC.
发明人： IANCU, Daniel , GLOSSNER, John, C. , HOKENEK, Erdem , MOUDGILL, Mayan , KOTLYAR, Vladimir
IPC分类号： G01S1/00
CPC分类号： G01S19/37 , G01S19/29 , Y10S367/904
摘要： A receiver includes a controller which receives A/D sampled input signals and shifts the sampled digital signal to compensate for Doppler effect in the input signal prior to demodulation. The controller compensates for a Doppler increased frequency by shifting the sampled digital signal so as to skip a sample period every n samples. This may be achieved by decreasing a cycle of m samples by one sample period every n samples. The controller compensates for a Doppler decreased frequency by shifting the sampled digital signal so as to add a sample period every n samples. This may be achieved by repeating a sample every n samples to shift the sampled digital signal. The compensation is performed in software on a multi-threaded processor.
摘要翻译：接收机包括控制器，其接收A / D采样输入信号并移位采样的数字信号以补偿在解调之前的输入信号中的多普勒效应。控制器通过移位采样的数字信号来补偿多普勒增加的频率，以便每n个样本跳过采样周期。这可以通过每n个样本减少一个采样周期的m个采样来实现。控制器通过移位采样的数字信号来补偿多普勒降低的频率，以便每n个样本添加采样周期。这可以通过每n个样本重复样本来实现，以移位采样的数字信号。补偿在多线程处理器的软件中执行。

5. 发明申请

WO2004054115A1 PARALLELIZED SLIDING-WINDOW MAP DECODING 审中-公开
标题翻译：并行滑动窗口地图解码
公开(公告)号：WO2004054115A1
公开(公告)日：2004-06-24
申请号：PCT/US2003/033584
申请日：2003-10-23
申请人： SANDBRIDGE TECHNOLOGIES, INC.
发明人： LU, Jin , CHUN, Joon-Hwa , HOKENEK, Erdem , MOUDGILL, Mayan
IPC分类号： H03M13/45
CPC分类号： H03M13/3927 , H03M13/296 , H03M13/6561 , H04L1/005 , H04L1/0066
摘要： A method of decoding using a log posterior probability ratio L(u k ), which is a function of forward variable α (.) and backward variable β (.) . The method comprises dividing the forward variable α (.) and the backward variable β (.) into, for example, two segments p and q , where p plus q equal the length of the code word U . The forward segments α (.) are parallel calculated, and the backward segments ,β (.) are parallel calculated. The ratio L(u k ) is calculated using the parallel calculated segments of α (.) and β (.).
摘要翻译：使用对数后验概率比L（uk）进行解码的方法，其是前向变量α（。）和向后变量β（。）的函数。该方法包括将前向变量α（。）和反向变量β（。）分成例如两个段p和q，其中p + q等于代码字U的长度。前向段α（。）并行计算，并且计算后向段β（。）。使用α（。）和β（。）的平行计算段计算比率L（uk）。

6. 发明申请

WO2003102780A1 METHOD AND APPARATUS FOR MULTITHREADED CACHE WITH CACHE EVICTION BASED ON THREAD IDENTIFIER 审中-公开
标题翻译：基于螺纹识别器的多速缓存高速缓存的方法和设备
公开(公告)号：WO2003102780A1
公开(公告)日：2003-12-11
申请号：PCT/US2003/017332
申请日：2003-06-03
申请人： SANDBRIDGE TECHNOLOGIES, INC.
发明人： HOKENEK, Erdem , GLOSSNER, John, C. , HOANE, Arthur, Joseph , MOUDGILL, Mayan , WANG, Shenghong
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , G06F12/0842 , G06F12/128
摘要： A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches (400’) each implementing a thread-based eviction process that reduces the amount of replacement policy storage required in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array (402) having multiple sets (set 1-set 4) of memory locations, and a directory (404) for storing tags (404-k) each corresponding to at least a portion of a particular address of one of the memory locations. The directory (404) has multiple entries each storing multiple ones of the tags (404-k), such that if there are n sets of memory locations in the memory array, there are n tags (404-k) associated with each directory entry. The directory (404) is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array. An entry in a particular one of the memory locations is selected for eviction from the given thread cache in conjunction with a cache miss event, based at least in part on at least a portion of a thread identifier of the given thread cache.
摘要翻译：用于多线程处理器的高速缓存存储器包括多个设置关联线程高速缓冲存储器，其中一个或多个线程高速缓冲存储器（400'）各自实现基于线程的逐出过程，该过程减少了在高速缓存存储器。在说明性实施例中的至少一个线程高速缓存中的给定的一个包括具有存储器位置的多个集合（集合1集合4）的存储器阵列（402）和用于存储每个对应的标签（404-k）的目录（404）到存储器位置之一的特定地址的至少一部分。目录（404）具有多个条目，每个条目存储多个标签（404-k），使得如果存储器阵列中存在n组存储器位置，则存在与每个目录条目相关联的n个标签（404-k）。目录（404）被用于实现访问请求和存储器阵列的存储器位置之间的集合关联地址映射。至少部分地基于给定线程高速缓存的线程标识符的至少一部分，选择存储器位置中的特定一个存储器位置中的入口与给定的线程高速缓存结合高速缓存未命中事件进行驱逐。

7. 发明申请

WO2003054714A1 MULTITHREADED PROCESSOR WITH EFFICIENT PROCESSING FOR CONVERGENCE DEVICE APPLICATIONS 审中-公开
标题翻译：具有高效处理功能的多功能处理器，适用于集成设备应用
公开(公告)号：WO2003054714A1
公开(公告)日：2003-07-03
申请号：PCT/US2002/039667
申请日：2002-12-11
申请人： SANDBRIDGE TECHNOLOGIES, INC.
发明人： HOKENEK, Erdem , MOUDGILL, Mayan , GLOSSNER, John, C.
IPC分类号： G06F15/00
CPC分类号： G06F9/3814 , G06F9/30036 , G06F9/30181 , G06F9/3802 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： A multithreaded processor includes an instruction decoder for decoding retrieved instructions to determine an instruction type for each of the retrieved instructions, an integer unit coupled to the instruction decoder for processing integer type instructions, and a vector unit coupled to the instruction decoder for processing vector type instructions. A reduction unit is preferably associated with the vector unit and receives parallel data elements processed in the vector unit. The reduction unit generates a serial output from the parallel data elements. The processor may be configured to execute at least control code, digital signal processor (DSP) code, Java code and network processing code, and is therefore well-suited for use in a convergence device. The processor is preferably configured to utilize token triggered threading in conjunction with instruction pipelining.
摘要翻译：多线程处理器包括用于对检索到的指令进行解码的指令解码器，以确定每个检索到的指令的指令类型，耦合到用于处理整数类型指令的指令解码器的整数单元，以及耦合到用于处理向量类型的指令解码器的向量单元说明。缩小单元优选地与矢量单元相关联并且接收在矢量单元中处理的并行数据元素。还原单元从并行数据元素生成串行输出。处理器可以被配置为至少执行控制代码，数字信号处理器DSP代码，Java代码和网络处理代码，因此非常适合用于收敛设备。处理器优选地被配置为结合指令流水线来利用令牌触发的线程。

8. 发明申请

WO2005101190A2 PROCESSOR HAVING PARALLEL VECTOR MULTIPLY AND REDUCE OPERATIONS WITH SEQUENTIAL SEMANTICS 审中-公开
标题翻译：具有并行矢量多项式和减少运算顺序语义的处理器
公开(公告)号：WO2005101190A2
公开(公告)日：2005-10-27
申请号：PCT/US2005/011976
申请日：2005-04-07
申请人： SANDBRIDGE TECHNOLOGIES, INC. , HOKENEK, Erdem , SCHULTE, Michael, J. , MOUDGILL, Mayan , GLOSSNER, John, C.
发明人： HOKENEK, Erdem , SCHULTE, Michael, J. , MOUDGILL, Mayan , GLOSSNER, John, C.
IPC分类号： G06F7/00
CPC分类号： G06F9/3001 , G06F7/49921 , G06F7/5443 , G06F2207/3828 , G06F2207/388
摘要： A processor comprises a plurality of arithmetic units, an accumulator unit, and a reduction unit coupled between the plurality of arithmetic units and the accumulator unit. The reduction unit receives products of vector elements from the arithmetic units and a first accumulator value from the accumulator unit, and processes the products and the first accumulator value to generate a second accumulator value for delivery to the accumulator unit. The processor implements a plurality of vector multiply and reduce operations having guaranteed sequential semantics, that is, operations which guarantee that the computational result will be the same as that which would be produced using a corresponding sequence of individual instructions.
摘要翻译：处理器包括多个运算单元，累加器单元和耦合在所述多个运算单元和所述累加器单元之间的缩减单元。还原单元从算术单元接收向量元素的乘积和来自累加器单元的第一累加器值，并且处理乘积和第一累加器值以产生用于递送到累加器单元的第二累加器值。处理器实现多个向量乘法和减少具有保证的顺序语义的操作，即，确保计算结果将与使用单独指令的相应序列产生的计算结果相同的操作。

9. 发明申请

WO2004036354A3 METHOD AND APPARATUS FOR HIGH SPEED CROSS-THREAD INTERRUPTS IN A MULTITHREADED PROCESSOR 审中-公开
公开(公告)号：WO2004036354A3
公开(公告)日：2004-04-29
申请号：PCT/US2003/032322
申请日：2003-10-10
申请人： SANDBRIDGE TECHNOLOGIES, INC.
发明人： HOKENEK, Erdem , MOUDGILL, Mayan , DORWARD, Sean, M.
IPC分类号： G06F9/46
摘要： A multithreaded processor includes an interrupt controller for processing a cross-thread interrupt directed from a requesting thread (512) to a destination thread (212). The interrupt controller in an illustrative embodiment receives a request (512) for delivery of the cross-thread interrupt to the destination thread (212), determines whether the destination thread of the cross-thread interrupt is enabled for receipt of cross-thread interrupts, and utilizes a thread identifier (212) to control delivery of the cross-thread interrupt to the destination thread (212) if the destination thread is enabled for receipt of cross-thread interrupts. The requesting thread requests delivery of the cross-thread interrupt to the destination thread by setting a corresponding interrupt pending bit in a flag register (400) of the multithreaded processor. The destination thread is enabled for receipt of cross-thread interrupts if a corresponding enable bit is set in an enable register (300) of the multithreaded processor. The flag and enable registers may be implemented within the interrupt controller.

10. 发明申请

WO2004034218A2 METHOD AND APPARATUS FOR THREAD-BASED MEMORY ACCESS IN A MULTITHREADED PROCESSOR 审中-公开
标题翻译：在多线程处理器中用于基于线程的存储器访问的方法和设备
公开(公告)号：WO2004034218A2
公开(公告)日：2004-04-22
申请号：PCT/US2003/031961
申请日：2003-10-09
申请人： SANDBRIDGE TECHNOLOGIES, INC.
发明人： HOKENEK, Erdem , MOUDGILL, Mayan , GLOSSNER, John, c.
IPC分类号： G06F
CPC分类号： G06F9/342 , G06F9/3851 , G06F12/06 , G06F12/0842 , G06F12/0846 , Y02D10/13
摘要： Techniques for thread-based memory access by a multithreaded processor are disclosed. The multithreaded processor determines a thread identifier associated with a particular processor thread, and utilizes at least a portion of the thread identifier to select a particular portion of an associated memory to be accessed by the corresponding processor thread. In an illustrative embodiment, a first portion of the thread identifier is utilized to select one of a plurality of multiple-bank memory elements within the memory, and a second portion of the thread identifier is utilized to select one of a plurality of memory banks within the selected one of the multiple-bank memory elements. The first portion may comprise one or more most significant bits of the thread identifier, while the second portion comprises one or more least significant bits of the thread identifier. Advantageously, the invention reduces memory access times and power consumption, while preventing the stalling of any processor threads.
摘要翻译：
披露了多线程处理器基于线程的内存访问技术。多线程处理器确定与特定处理器线程相关联的线程标识符，并且利用线程标识符的至少一部分来选择要由相应处理器线程访问的关联存储器的特定部分。在说明性实施例中，利用线程标识符的第一部分来选择存储器内的多个多存储体单元中的一个存储单元，并且利用线程标识符的第二部分来选择多个存储体中的一个存储体选择多个存储体元件中的一个。第一部分可以包括线程标识符的一个或多个最高有效位，而第二部分包括线程标识符的一个或多个最低有效位。有利地，本发明减少了存储器访问时间和功耗，同时防止了任何处理器线程的停顿。

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