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1. 发明申请

WO2016191155A1 METHOD OF FORMING MEMORY CELL WITH HIGH-K CHARGE TRAPPING LAYER 审中-公开
标题翻译：用高K电荷捕获层形成存储单元的方法
公开(公告)号：WO2016191155A1
公开(公告)日：2016-12-01
申请号：PCT/US2016/032927
申请日：2016-05-17
申请人： SANDISK TECHNOLOGIES LLC
发明人： RABKIN, Peter , PACHAMUTHU, Jayavel , ALSMEIER, Johann , HIGASHITANI, Masaaki
IPC分类号： H01L29/423 , H01L21/28 , H01L29/51 , H01L29/792
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/1157 , H01L29/4234 , H01L29/513 , H01L29/517
摘要： A non-volatile storage device with memory cells having a high-k charge storage region, as well as methods of fabrication, is disclosed. The charge storage region has three or more layers of dielectric materials. At least one layer is a high-k material. The high-k layer(s) has a higher trap density as compared to S13N4. High-k dielectrics in the charge storage region enhance capacitive coupling with the memory cell channel, which can improve memory cell current, program speed, and erase speed. The charge storage region has a high-low-high conduction band offset, which may improve data retention. The charge storage region has a low-high-low valence band offset, which may improve erase.
摘要翻译：公开了具有高k电荷存储区域的存储单元以及制造方法的非易失性存储装置。电荷存储区域具有三层或更多层介电材料。至少一层是高k材料。与S13N4相比，高k层具有更高的陷阱密度。电荷存储区域中的高k电介质增强了与存储单元通道的电容耦合，这可以提高存储单元电流，编程速度和擦除速度。电荷存储区具有高 - 低 - 高导带偏移，这可以改善数据保留。电荷存储区域具有低 - 高 - 低价带偏移，这可以改善擦除。

2. 发明申请

WO2016191156A1 MEMORY CELL WITH HIGH-K CHARGE TRAPPING LAYER 审中-公开
标题翻译：具有高K电荷捕获层的存储单元
公开(公告)号：WO2016191156A1
公开(公告)日：2016-12-01
申请号：PCT/US2016/032928
申请日：2016-05-17
申请人： SANDISK TECHNOLOGIES LLC
发明人： RABKIN, Peter , PACHAMUTHU, Jayavel , ALSMEIER, Johann , HIGASHITANI, Masaaki
IPC分类号： H01L29/423 , H01L21/28 , H01L29/51 , H01L29/792
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/1157 , H01L29/4234 , H01L29/513 , H01L29/517 , H01L29/7926
摘要： A non-volatile storage device with memory cells having a high-k charge storage region, as well as methods of fabrication, is disclosed. The charge storage region has three or more layers of dielectric materials. At least one layer is a high-k material. The high-k layer(s) has a higher trap density as compared to S13N4. High-k dielectrics in the charge storage region enhance capacitive coupling with the memory cell channel, which can improve memory cell current, program speed, and erase speed. The charge storage region has a high-low-high conduction band offset, which may improve data retention. The charge storage region has a low-high-low valence band offset, which may improve erase.
摘要翻译：公开了具有高k电荷存储区域的存储单元以及制造方法的非易失性存储装置。电荷存储区域具有三层或更多层介电材料。至少一层是高k材料。与S13N4相比，高k层具有更高的陷阱密度。电荷存储区域中的高k电介质增强了与存储单元通道的电容耦合，这可以提高存储单元电流，编程速度和擦除速度。电荷存储区具有高 - 低 - 高导带偏移，这可以改善数据保留。电荷存储区域具有低 - 高 - 低价带偏移，这可以改善擦除。

3. 发明申请

WO2016164213A1 THREE-DIMENSIONAL INTEGRATION SCHEMES FOR REDUCING FLUORINE-INDUCED ELECTRICAL SHORTS 审中-公开
标题翻译：降低氟诱导电气短路的三维集成方案
公开(公告)号：WO2016164213A1
公开(公告)日：2016-10-13
申请号：PCT/US2016/024784
申请日：2016-03-29
申请人： SANDISK TECHNOLOGIES LLC
发明人： PACHAMUTHU, Jayavel , BAENNINGER, Matthias , SHI, Stephen , ALSMEIER, Johann
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L21/768 , H01L23/5226 , H01L23/528 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/7883
摘要： Dielectric degradation and electrical shorts due to fluorine radical generation from metallic electrically conductive lines in a three-dimensional memory device can be reduced by forming composite electrically conductive layers and/or use of a metal oxide material for an insulating spacer for backside contact trenches. Each composite electrically conductive layer includes a doped semiconductor material portion in proximity to memory stack structures and a metallic material portion in proximity to a backside contact trench. Fluorine generated from the metallic material layers can escape readily through the backside contact trench. The semiconductor material portions can reduce mechanical stress. Alternatively or additionally, a dielectric metal oxide employed as an insulating spacer formed on the sidewalls of the backside contact trench, thereby blocking a diffusion path for fluorine radicals generated from the metallic material of the electrically conductive layers, and preventing electrical shorts between electrically conductive layers and/or a backside contact via structure.
摘要翻译：通过形成复合导电层和/或使用用于背面接触沟槽的绝缘间隔物的金属氧化物材料，可以减少由于三维存储器件中的金属导电线产生氟自由基引起的介电性劣化和电短路。每个复合导电层包括靠近存储堆叠结构的掺杂半导体材料部分和靠近背面接触沟槽的金属材料部分。从金属材料层产生的氟可以容易地通过背面接触沟槽逸出。半导体材料部分可以减小机械应力。或者或另外，用作绝缘间隔物的电介质金属氧化物形成在背侧接触沟槽的侧壁上，从而阻挡由导电层的金属材料产生的氟自由基的扩散路径，并防止导电层之间的电短路和/或背面接触通孔结构。

4. 发明申请

WO2017172072A1 NAND STRUCTURE WITH TIER SELECT GATE TRANSISTORS 审中-公开
标题翻译：带有选择栅极晶体管的NAND结构
公开(公告)号：WO2017172072A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/017630
申请日：2017-02-13
申请人： SANDISK TECHNOLOGIES LLC
发明人： SABDE, Jagdish , PACHAMUTHU, Jayavel , RABKIN, Peter
IPC分类号： G11C16/04 , G11C16/34 , G11C16/10 , G11C16/16 , G11C11/56
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5635 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16
摘要： Systems and methods for improving performance of a non-volatile memory by utilizing one or more tier select gate transistors between different portions of a NAND string are described. A first memory string tier may comprise a first set of memory cell transistors that may be programmed to store a first set of data and a second memory string tier may comprise a second set of memory cell transistors that are arranged above the first set of transistors and that may be programmed to store a second set of data. Between the first set of memory cell transistors and the second set of memory cell transistors may comprise a tier select gate transistor in series with the first set of memory cell transistors and the second set of memory cell transistors. The tier select gate transistor may comprise a programmable transistor or a non-programmable transistor.
摘要翻译：描述了通过利用NAND串的不同部分之间的一个或多个层选择门晶体管来提高非易失性存储器的性能的系统和方法。第一存储器串层可以包括可以被编程以存储第一组数据的第一组存储器单元晶体管，并且第二存储器串层可以包括被布置在第一组晶体管上方的第二组存储器单元晶体管，以及其可以被编程为存储第二组数据。在第一组存储器单元晶体管和第二组存储器单元晶体管之间可以包括与第一组存储器单元晶体管和第二组存储器单元晶体管串联的层选择栅极晶体管。层选择栅晶体管可以包括可编程晶体管或不可编程晶体管。

5. 发明申请

WO2023022767A1 NON-VOLATILE MEMORY WITH EFFICIENT TESTING DURING ERASE 审中-公开
公开(公告)号：WO2023022767A1
公开(公告)日：2023-02-23
申请号：PCT/US2022/028225
申请日：2022-05-07
申请人： SANDISK TECHNOLOGIES LLC
发明人： PACHAMUTHU, Jayavel , SUBRAMANIAN, Ramkumar
IPC分类号： G11C16/34 , G11C16/14 , G11C16/08 , G11C16/24 , G11C16/04
摘要： A non-volatile memory system erasing groups of connected memory cells separately performs erase verify for memory cells connected to even word lines to generate even results and erase verify for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine if the erase verify process indicates that the erasing has successful completed. In addition, for each group of connected memory cells, a last even result for the group is compared to a last odd result for the group. Even if the erase verify indicated that the erasing has successfully completed, the system may determine that the erasing failed (i.e. due to a defect) if the number of groups of connected memory cells that have the last even result different than the last odd result is greater than a limit.

6. 发明申请

WO2017222605A1 AMORPHOUS SILICON LAYER IN MEMORY DEVICE WHICH REDUCES NEIGHBORING WORD LINE INTERFERENCE 审中-公开
标题翻译：存储设备中减少相邻字词干扰的非晶硅层
公开(公告)号：WO2017222605A1
公开(公告)日：2017-12-28
申请号：PCT/US2017/018759
申请日：2017-02-21
申请人： SANDISK TECHNOLOGIES LLC
发明人： PANG, Liang , PACHAMUTHU, Jayavel , DONG, Yingda
IPC分类号： H01L29/66 , H01L29/788 , H01L29/792 , H01L27/11548 , H01L27/11563 , H01L27/11556 , H01L27/11582
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/0217 , H01L21/02238 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/02667 , H01L21/31111 , H01L27/11568 , H01L29/40117 , H01L29/42368 , H01L29/66545 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/7926
摘要： Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, rounding off of the control gate layers due to inadvertent oxidation during fabrication is avoided. An amorphous silicon layer is deposited along the sidewall of the memory holes, adjacent to the control gate layers. Si 3 N 4 is deposited along the amorphous silicon layer and oxidized in the memory hole to form SiO 2 . The amorphous silicon layer acts as an oxidation barrier for the sacrificial material of the control gate layers. The amorphous silicon layer is subsequently oxidized to also form SiO 2 . The two SiO 2 layers together form a blocking oxide layer.
摘要翻译：制造具有减小的邻近字线干扰的存储器件的技术以及相应的存储器件。存储器件包括交替的导电层和介电层的堆叠，其中导电层形成存储器单元的字线或控制栅极。在一个方面中，避免了由于在制造期间的意外氧化而使控制栅极层四舍五入。非晶硅层沿存储器孔的侧壁沉积，与控制栅极层相邻。 Si 3 N 4沿非晶硅层沉积并在记忆孔中氧化形成SiO 2。非晶硅层充当用于控制栅极层的牺牲材料的氧化阻挡层。随后将非晶硅层氧化以形成SiO 2 2。两个SiO 2层一起形成阻挡氧化层。

7. 发明申请

WO2016175979A1 MULTILEVEL MEMORY STACK STRUCTURE EMPLOYING SUPPORT PILLAR STRUCTURES 审中-公开
标题翻译：多层记忆体结构采用支撑支柱结构
公开(公告)号：WO2016175979A1
公开(公告)日：2016-11-03
申请号：PCT/US2016/025409
申请日：2016-03-31
申请人： SANDISK TECHNOLOGIES LLC
发明人： LIU, Jin , ZHANG, Tong , PACHAMUTHU, Jayavel , LEE, Yao-Sheng , ALSMEIER, Johann
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L21/76802 , H01L21/76877 , H01L23/528 , H01L27/11526 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L29/41741 , H01L29/7883
摘要： A first stack of alternating layers including first electrically insulating layers and first sacrificial material layers is formed with first stepped surfaces. First memory openings can be formed in a device region outside of the first stepped surfaces, and first support openings can be formed through the first stepped surfaces. The first memory openings and the first support openings can be filled with a sacrificial fill material. A second stack of alternating layers including second electrically insulating layers and second sacrificial material layers can be formed over the first stack. Inter-stack memory openings including the first memory openings can be formed in the device region, and inter-stack support openings including the first support openings can be formed in a steppes surface region. Memory stack structures and support pillar structure are simultaneously formed in the inter-stack memory openings and the inter-stack support openings, respectively.
摘要翻译：包括第一电绝缘层和第一牺牲材料层的交替层的第一堆叠形成有第一台阶表面。第一存储器开口可以形成在第一台阶表面外部的器件区域中，并且可以通过第一台阶表面形成第一支撑开口。第一存储器开口和第一支撑开口可以填充牺牲填充材料。可以在第一堆叠上形成包括第二电绝缘层和第二牺牲材料层的交替层的第二堆叠。包括第一存储器开口的堆叠间存储器开口可以形成在器件区域中，并且包括第一支撑开口的堆叠间支撑开口可以形成在草原表面区域中。存储堆叠结构和支撑柱结构分别同时形成在堆叠间存储器开口和堆叠间支撑开口中。

8. 发明公开

EP3262690A1 MEMORY CELL WITH HIGH-K CHARGE TRAPPING LAYER 有权
标题翻译：具有高K电荷陷阱层的存储器单元
公开(公告)号：EP3262690A1
公开(公告)日：2018-01-03
申请号：EP16726462.1
申请日：2016-05-17
申请人： SanDisk Technologies LLC
发明人： RABKIN, Peter , PACHAMUTHU, Jayavel , ALSMEIER, Johann , HIGASHITANI, Masaaki
IPC分类号： H01L29/423 , H01L21/28 , H01L29/51 , H01L29/792
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/1157 , H01L29/4234 , H01L29/513 , H01L29/517 , H01L29/7926
摘要： A non-volatile storage device with memory cells having a high-k charge storage region, as well as methods of fabrication, is disclosed. The charge storage region has three or more layers of dielectric materials. At least one layer is a high-k material. The high-k layer(s) has a higher trap density as compared to Si3N4. High-k dielectrics in the charge storage region enhance capacitive coupling with the memory cell channel, which can improve memory cell current, program speed, and erase speed. The charge storage region has a high-low-high conduction band offset, which may improve data retention. The charge storage region has a low-high-low valence band offset, which may improve erase.

9. 发明公开

EP3210235A2 THREE DIMENSIONAL NAND STRING MEMORY DEVICES AND METHODS OF FABRICATION THEREOF 有权
标题翻译：三维NAND串存储器件及其制造方法
公开(公告)号：EP3210235A2
公开(公告)日：2017-08-30
申请号：EP15778808.4
申请日：2015-09-21
申请人： SanDisk Technologies LLC
发明人： PACHAMUTHU, Jayavel , ALSMEIER, Johann , CHIEN, Henry
IPC分类号： H01L21/28 , H01L27/115 , H01L21/02
CPC分类号： H01L27/11556 , H01L21/02164 , H01L21/0217 , H01L21/02244 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/02667 , H01L21/02672 , H01L21/28273 , H01L21/28282 , H01L21/28556 , H01L21/28568 , H01L21/31111 , H01L27/11524 , H01L27/1157 , H01L27/11582 , H01L29/42328 , H01L29/42344 , H01L29/4916 , H01L29/4966 , H01L29/7883
摘要： Monolithic three-dimensional NAND memory strings and methods of fabricating a monolithic three-dimensional NAND memory string include forming single crystal or large grain polycrystalline semiconductor material charge storage regions by a metal induced crystallization process. In another embodiment, a plurality of front side recesses are formed having a concave-shaped surface and a blocking dielectric and charge storage regions are formed within the front side recesses and over the concave-shaped surface. In another embodiment, layers of oxide material exposed in a front side opening of a material layer stack are surface nitrided and etched to provide convexly-rounded corner portions, and a blocking dielectric is formed over the convexly-rounded corner portions.
摘要翻译：一种方法包括在前侧开口的侧壁的至少一部分上以及在交替的第一和第二材料层的堆叠中的前侧凹槽内形成非晶或多晶半导体材料，在至少一个交替的第一和第二材料层上形成金属材料层所述前侧开口的所述侧壁的一部分并且在所述前侧凹槽内与所述半导体材料相邻; 通过金属诱导结晶工艺在前侧凹槽内对金属材料和半导体材料进行退火以在每个前侧凹槽内形成大晶粒多晶或单晶半导体材料电荷储存区域，以及形成隧道介电层和半导体沟道在前侧开口。在金属诱导结晶过程之后，至少一部分金属材料位于电荷存储区域和第二材料层之间。

10. 发明公开

EP3262689A1 METHOD OF FORMING MEMORY CELL WITH HIGH-K CHARGE TRAPPING LAYER 有权
标题翻译：用高K电荷陷阱层形成存储器单元的方法
公开(公告)号：EP3262689A1
公开(公告)日：2018-01-03
申请号：EP16726461.3
申请日：2016-05-17
申请人： SanDisk Technologies LLC
发明人： RABKIN, Peter , PACHAMUTHU, Jayavel , ALSMEIER, Johann , HIGASHITANI, Masaaki
IPC分类号： H01L29/423 , H01L21/28 , H01L29/51 , H01L29/792
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/1157 , H01L29/4234 , H01L29/513 , H01L29/517
摘要： A non-volatile storage device with memory cells having a high-k charge storage region, as well as methods of fabrication, is disclosed. The charge storage region has three or more layers of dielectric materials. At least one layer is a high-k material. The high-k layer(s) has a higher trap density as compared to Si3N4. High-k dielectrics in the charge storage region enhance capacitive coupling with the memory cell channel, which can improve memory cell current, program speed, and erase speed. The charge storage region has a high-low-high conduction band offset, which may improve data retention. The charge storage region has a low-high-low valence band offset, which may improve erase.

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