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1. 发明申请

WO2016164213A1 THREE-DIMENSIONAL INTEGRATION SCHEMES FOR REDUCING FLUORINE-INDUCED ELECTRICAL SHORTS 审中-公开
标题翻译：降低氟诱导电气短路的三维集成方案
公开(公告)号：WO2016164213A1
公开(公告)日：2016-10-13
申请号：PCT/US2016/024784
申请日：2016-03-29
申请人： SANDISK TECHNOLOGIES LLC
发明人： PACHAMUTHU, Jayavel , BAENNINGER, Matthias , SHI, Stephen , ALSMEIER, Johann
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L21/768 , H01L23/5226 , H01L23/528 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/7883
摘要： Dielectric degradation and electrical shorts due to fluorine radical generation from metallic electrically conductive lines in a three-dimensional memory device can be reduced by forming composite electrically conductive layers and/or use of a metal oxide material for an insulating spacer for backside contact trenches. Each composite electrically conductive layer includes a doped semiconductor material portion in proximity to memory stack structures and a metallic material portion in proximity to a backside contact trench. Fluorine generated from the metallic material layers can escape readily through the backside contact trench. The semiconductor material portions can reduce mechanical stress. Alternatively or additionally, a dielectric metal oxide employed as an insulating spacer formed on the sidewalls of the backside contact trench, thereby blocking a diffusion path for fluorine radicals generated from the metallic material of the electrically conductive layers, and preventing electrical shorts between electrically conductive layers and/or a backside contact via structure.
摘要翻译：通过形成复合导电层和/或使用用于背面接触沟槽的绝缘间隔物的金属氧化物材料，可以减少由于三维存储器件中的金属导电线产生氟自由基引起的介电性劣化和电短路。每个复合导电层包括靠近存储堆叠结构的掺杂半导体材料部分和靠近背面接触沟槽的金属材料部分。从金属材料层产生的氟可以容易地通过背面接触沟槽逸出。半导体材料部分可以减小机械应力。或者或另外，用作绝缘间隔物的电介质金属氧化物形成在背侧接触沟槽的侧壁上，从而阻挡由导电层的金属材料产生的氟自由基的扩散路径，并防止导电层之间的电短路和/或背面接触通孔结构。

2. 发明申请

WO2018017181A1 THREE-DIMENSIONAL MEMORY DEVICE WITH SELECT TRANSISTOR HAVING CHARGE TRAPPING GATE DIELECTRIC LAYER AND METHODS OF MAKING AND OPERATING THEREOF 审中-公开
标题翻译：具有选择晶体管的三维存储器装置，具有电荷捕获闸极介电层及其制造和操作方法
公开(公告)号：WO2018017181A1
公开(公告)日：2018-01-25
申请号：PCT/US2017/032727
申请日：2017-05-15
申请人： SANDISK TECHNOLOGIES LLC
发明人： BARASKAR, Ashish , ZHANG, Yanli , PANG, Liang , LU, Ching-Huang , BAENNINGER, Matthias , DONG, Yingda
IPC分类号： H01L27/1157 , H01L27/11582
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/02271 , H01L27/1157 , H01L29/40117
摘要： A gate dielectric layer including a tunneling gate dielectric layer, a charge trapping gate dielectric layer, and a cap gate dielectric layer is formed on a horizontal semiconductor channel. An alternating stack of insulating layers and spacer material layers is formed over the gate dielectric layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conducive layers. Memory stack structures are formed through the alternating stack and the gate dielectric layer. Electrical charges can be injected into the charge trapping gate dielectric layer from the horizontal semiconductor channel to program the threshold voltage of a select field effect transistor employing a bottommost electrically conductive layer as a select gate electrode. The programmable threshold voltage can be advantageously employed to provide enhanced electrical isolation among word lines.
摘要翻译：在水平半导体沟道上形成包括隧穿栅极电介质层，电荷俘获栅极电介质层和帽栅极电介质层的栅极电介质层。在栅介质层上形成交替的绝缘层和间隔材料层的叠层。间隔物材料层形成为导电层或随后替换为导电层。存储器堆叠结构通过交替堆叠和栅极电介质层形成。可以将电荷从水平半导体沟道注入到电荷俘获栅极介电层中，以将采用最底部导电层的选择场效应晶体管的阈值电压编程为选择栅电极。可编程的阈值电压可以有利地用于提供字线之间的增强的电隔离。

3. 发明公开

EP3152783A1 THREE DIMENSIONAL NAND DEVICE HAVING A WAVY CHARGE STORAGE LAYER 审中-公开
标题翻译： DREIDIMENSIONALE NAND-VORRICHTUNG MITWELLENFÖRMIGERLADUNGSSPEICHERUNGSSCHICHT
公开(公告)号：EP3152783A1
公开(公告)日：2017-04-12
申请号：EP15727191.7
申请日：2015-05-20
申请人： SanDisk Technologies LLC
发明人： ZHANG, Yanli , BAENNINGER, Matthias , MATSUDAIRA, Akira , LEE, Yao-Sheng , ALSMEIER, Johann
IPC分类号： H01L27/115
CPC分类号： H01L29/1029 , H01L27/1157 , H01L27/11582
摘要： A monolithic three dimensional NAND string includes a semiconductor channel, where at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, an interlevel insulating layer located between adjacent control gate electrodes, a blocking dielectric layer located in contact with the plurality of control gate electrodes and an interlevel insulating layer, a charge storage layer located at least partially in contact with the blocking dielectric layer, and a tunnel dielectric located between the charge storage layer and the semiconductor channel. The charge storage layer has a curved profile.
摘要翻译：单片三维NAND串包括半导体沟道，其中半导体沟道的至少一个端部基本上垂直于衬底的主表面延伸，多个基本上平行于衬底的主表面延伸的控制栅电极，位于相邻的控制栅极之间的层间绝缘层，与多个控制栅电极接触的阻挡介电层和层间绝缘层，至少部分地与阻挡介电层接触的电荷存储层，以及隧道电介质位于电荷存储层和半导体沟道之间。电荷存储层具有弯曲轮廓。

4. 发明公开

EP3218931A1 THREE DIMENSIONAL NAND DEVICE HAVING REDUCED WAFER BOWING AND METHOD OF MAKING THEREOF 有权
标题翻译：具有减小的晶圆弓的三维NAND器件及其制造方法
公开(公告)号：EP3218931A1
公开(公告)日：2017-09-20
申请号：EP15777829.1
申请日：2015-09-28
申请人： SanDisk Technologies LLC
发明人： BAENNINGER, Matthias , PACHAMUTHU, Jayavel , ALSMEIER, Johann
IPC分类号： H01L27/115 , H01L23/00
CPC分类号： H01L29/7846 , H01L23/562 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, and at least one trench extending substantially perpendicular to the major surface of the substrate. The trench is filled with at least a first trench material and a second trench material. The first trench material includes a material under a first magnitude of a first stress type, and the second trench material includes a material under no stress, a second stress type opposite the first stress type, or a second magnitude of the first stress type lower than the first magnitude of the first stress type to offset warpage of the substrate due to the stress imposed by at least one of the first trench material or the plurality of control gate electrodes on the substrate.
摘要翻译：单片三维NAND串包括基本上平行于衬底的主表面延伸的多个控制栅电极以及基本上垂直于衬底的主表面延伸的至少一个沟槽。沟槽填充有至少第一沟槽材料和第二沟槽材料。第一沟槽材料包括处于第一应力类型的第一量值下的材料，并且第二沟槽材料包括无应力下的材料，与第一应力类型相反的第二应力类型或者低于第一应力类型的第二量值所述第一应力类型的第一量值用于抵消由所述第一沟槽材料或所述多个控制栅电极中的至少一个施加在所述衬底上的应力引起的所述衬底的翘曲。

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