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1. 发明申请

US20090013206A1 Efficient Utilization of a Multi-Source Network of Control Logic to Achieve Timing Closure in a Clocked Logic Circuit 有权
标题翻译：控制逻辑的多源网络的高效利用在时钟逻辑电路中实现定时闭合
公开(公告)号：US20090013206A1
公开(公告)日：2009-01-08
申请号：US11772908
申请日：2007-07-03
申请人： Lawrence D. Curley , John M. Isakson , Arjen Mets , Travis W. Pouarz , Thomas E. Rosser , Kristen M. Tucker
发明人： Lawrence D. Curley , John M. Isakson , Arjen Mets , Travis W. Pouarz , Thomas E. Rosser , Kristen M. Tucker
IPC分类号： G06F1/14
CPC分类号： G06F17/505 , G06F2217/62
摘要： A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于实现时钟逻辑电路中的定时关闭。对于一组本地时钟缓冲器中的每个本地时钟缓冲器，逻辑综合工具确定从一组时钟控制信号输入端输入的时钟控制信号，该时钟控制信号输入将以目标频率将时钟控制信号驱动到本地时钟缓冲器，可以满足第一时间约束。由逻辑综合工具执行的操作形成确定的时钟控制信号输入。响应于确定所确定的时钟控制信号输入的逻辑综合工具，逻辑综合工具将本地时钟缓冲器耦合到所确定的时钟控制信号输入端，该时钟控制信号输入以目标频率驱动时钟控制信号到本地时钟缓冲器，以实现定时闭合时钟逻辑电路。

2. 发明授权

US07979732B2 Efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuit 有权
标题翻译：有效利用控制逻辑的多源网络来实现时钟逻辑电路中的时序闭合
公开(公告)号：US07979732B2
公开(公告)日：2011-07-12
申请号：US11772908
申请日：2007-07-03
申请人： Lawrence D. Curley , John M. Isakson , Arjen Mets , Travis W. Pouarz , Thomas E. Rosser , Kristen M. Tucker
发明人： Lawrence D. Curley , John M. Isakson , Arjen Mets , Travis W. Pouarz , Thomas E. Rosser , Kristen M. Tucker
IPC分类号： G06F1/12 , G06F1/14
CPC分类号： G06F17/505 , G06F2217/62
摘要： A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于实现时钟逻辑电路中的定时关闭。对于一组本地时钟缓冲器中的每个本地时钟缓冲器，逻辑综合工具确定从一组时钟控制信号输入端输入的时钟控制信号，该时钟控制信号输入将以目标频率将时钟控制信号驱动到本地时钟缓冲器，可以满足第一时间约束。由逻辑综合工具执行的操作形成确定的时钟控制信号输入。响应于确定所确定的时钟控制信号输入的逻辑综合工具，逻辑综合工具将本地时钟缓冲器耦合到所确定的时钟控制信号输入端，该时钟控制信号输入以目标频率驱动时钟控制信号到本地时钟缓冲器，以实现定时闭合时钟逻辑电路。

3. 发明授权

US08688880B2 Centralized serialization of requests in a multiprocessor system 失效
标题翻译：在多处理器系统中集中序列化请求
公开(公告)号：US08688880B2
公开(公告)日：2014-04-01
申请号：US12821933
申请日：2010-06-23
申请人： Garrett M. Drapala , Michael A. Blake , Timothy C. Bronson , Lawrence D. Curley
发明人： Garrett M. Drapala , Michael A. Blake , Timothy C. Bronson , Lawrence D. Curley
IPC分类号： G06F12/00 , G06F13/14 , G06F13/38
CPC分类号： G06F9/526 , G06F2209/522
摘要： Serializing instructions in a multiprocessor system includes receiving a plurality of processor requests at a central point in the multiprocessor system. Each of the plurality of processor requests includes a needs register having a requestor needs switch and a resource needs switch. The method also includes establishing a tail switch indicating the presence of the plurality of processor requests at the central point, establishing a sequential order of the plurality of processor requests, and processing the plurality of processor requests at the central point in the sequential order.
摘要翻译：在多处理器系统中串行化指令包括在多处理器系统的中心点处接收多个处理器请求。多个处理器请求中的每一个包括具有请求者需求切换和资源需要切换的需求寄存器。该方法还包括建立指示在中心点存在多个处理器请求的尾部开关，建立多个处理器请求的顺序，以及按照顺序在中心点处理多个处理器请求。

4. 发明授权

US06198772B1 Motion estimation processor for a digital video encoder 失效
标题翻译：用于数字视频编码器的运动估计处理器
公开(公告)号：US06198772B1
公开(公告)日：2001-03-06
申请号：US08996856
申请日：1997-12-23
申请人： Charles E. Boice , Lawrence D. Curley , John M. Kaczmarczyk , Agnes Y. Ngai , Charles J. Stein
发明人： Charles E. Boice , Lawrence D. Curley , John M. Kaczmarczyk , Agnes Y. Ngai , Charles J. Stein
IPC分类号： H04N750
CPC分类号： H04N19/423 , H04N5/147 , H04N11/044 , H04N11/20 , H04N19/42 , H04N19/61
摘要： A digital video encoder system having a motion estimation processor, and an interface to the motion estimation processor. The motion estimation processor includes a reference memory interface, and inverse quantization processor, an inverse discrete cosine transform processor, and a motion estimation processor unit including a hierarchal search unit. The motion estimation processor is utilized generating temporally compressed datastreams, that is, I-P and I-P-B datastreams.
摘要翻译：一种具有运动估计处理器的数字视频编码器系统以及与运动估计处理器的接口。运动估计处理器包括参考存储器接口和逆量化处理器，反相离散余弦变换处理器，以及包括分级搜索单元的运动估计处理器单元。使用运动估计处理器来生成时间压缩的数据流，即I-P和I-P-B数据流。

5. 发明授权

US08364904B2 Horizontal cache persistence in a multi-compute node, symmetric multiprocessing computer 失效
标题翻译：多计算节点，对称多处理计算机中的水平缓存持久性
公开(公告)号：US08364904B2
公开(公告)日：2013-01-29
申请号：US12819348
申请日：2010-06-21
申请人： Michael A. Blake , Lawrence D. Curley , Garrett M. Drapala , Edward J. Kaminski , Craig R. Walters
发明人： Michael A. Blake , Lawrence D. Curley , Garrett M. Drapala , Edward J. Kaminski , Craig R. Walters
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/084
摘要： Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of the cache line receiving compute nodes, including, if the cache line is missing from a compute node, an indication whether that compute node has cache storage space available for the cache line; determining by the first compute node, according to the states of the cache line and space available, whether the first compute node can evict the cache line without writing the cache line to main memory; and updating by each compute node the state of the cache line in each compute node, in dependence upon one or more of the states of the cache line in all the compute nodes.
摘要翻译：包括在多计算节点SMP计算机中的水平缓存持续性，包括响应于在计算节点的第一个计算节点上驱逐高速缓存行的确定，由第一计算节点广播高速缓存行的逐出通知; 发送接收计算节点的高速缓存行的状态，包括如果高速缓存线从计算节点丢失，则指示该计算节点是否具有可用于高速缓存行的高速缓存存储空间; 由所述第一计算节点根据所述高速缓存行的状态和可用空间来确定所述第一计算节点是否可以驱逐所述高速缓存行而不将高速缓存行写入主存储器; 并且根据所有计算节点中的高速缓存行的一个或多个状态，由每个计算节点更新每个计算节点中的高速缓存行的状态。

6. 发明申请

US20110314227A1 Horizontal Cache Persistence In A Multi-Compute Node, Symmetric Multiprocessing Computer 失效
标题翻译：多计算节点中的水平缓存持久性，对称多处理计算机
公开(公告)号：US20110314227A1
公开(公告)日：2011-12-22
申请号：US12819348
申请日：2010-06-21
申请人： Michael A. Blake , Lawrence D. Curley , Garrett M. Drapala , Edward J. Kaminski, JR. , Craig R. Walters
发明人： Michael A. Blake , Lawrence D. Curley , Garrett M. Drapala , Edward J. Kaminski, JR. , Craig R. Walters
IPC分类号： G06F12/08
CPC分类号： G06F12/127 , G06F12/084
摘要： Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of the cache line receiving compute nodes, including, if the cache line is missing from a compute node, an indication whether that compute node has cache storage space available for the cache line; determining by the first compute node, according to the states of the cache line and space available, whether the first compute node can evict the cache line without writing the cache line to main memory; and updating by each compute node the state of the cache line in each compute node, in dependence upon one or more of the states of the cache line in all the compute nodes.
摘要翻译：包括在多计算节点SMP计算机中的水平缓存持续性，包括响应于在计算节点的第一个计算节点上驱逐高速缓存行的确定，由第一计算节点广播高速缓存行的逐出通知; 发送接收计算节点的高速缓存行的状态，包括如果高速缓存线从计算节点丢失，则指示该计算节点是否具有可用于高速缓存行的高速缓存存储空间; 由所述第一计算节点根据所述高速缓存行的状态和可用空间来确定所述第一计算节点是否可以驱逐所述高速缓存行而不将高速缓存行写入主存储器; 并且根据所有计算节点中的高速缓存行的一个或多个状态，由每个计算节点更新每个计算节点中的高速缓存行的状态。

7. 发明授权

US08479070B2 Integrated circuit arrangement for test inputs 有权
标题翻译：用于测试输入的集成电路布置
公开(公告)号：US08479070B2
公开(公告)日：2013-07-02
申请号：US12822287
申请日：2010-06-24
申请人： Ulrich Baur , Lawrence D. Curley , Ronald J. Frishmuth , Ralf Ludewig , Ching L. Tong , Tobias Webel
发明人： Ulrich Baur , Lawrence D. Curley , Ronald J. Frishmuth , Ralf Ludewig , Ching L. Tong , Tobias Webel
IPC分类号： G01R31/28
CPC分类号： G01R31/31701 , G01R31/3172
摘要： An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.
摘要翻译：集成电路芯片包括通信地连接到第一输入/输出（I / O）引脚的主线功能逻辑路径，通信地连接到第一I / O引脚的测试逻辑路径，设置在测试逻辑之间的通信连接之间的锁存器功能路径和第一I / O引脚，第二I / O引脚通信地连接到锁存器，第二I / O引脚可操作以发送操作以改变锁存器的状态的信号。

8. 发明申请

US20110320898A1 Integrated Circuit Arrangement For Test Inputs 有权
标题翻译：用于测试输入的集成电路布置
公开(公告)号：US20110320898A1
公开(公告)日：2011-12-29
申请号：US12822287
申请日：2010-06-24
申请人： Ulrich Baur , Lawrence D. Curley , Ronald J. Frishmuth , Ralf Ludewig , Ching L. Tong , Tobias Webel
发明人： Ulrich Baur , Lawrence D. Curley , Ronald J. Frishmuth , Ralf Ludewig , Ching L. Tong , Tobias Webel
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31701 , G01R31/3172
摘要： An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.
摘要翻译：集成电路芯片包括通信地连接到第一输入/输出（I / O）引脚的主线功能逻辑路径，通信地连接到第一I / O引脚的测试逻辑路径，设置在测试逻辑之间的通信连接之间的锁存器功能路径和第一I / O引脚，第二I / O引脚通信地连接到锁存器，第二I / O引脚可操作以发送操作以改变锁存器的状态的信号。

9. 发明申请

US20110320778A1 CENTRALIZED SERIALIZATION OF REQUESTS IN A MULTIPROCESSOR SYSTEM 失效
标题翻译：多处理器系统中的要求的集中串行化
公开(公告)号：US20110320778A1
公开(公告)日：2011-12-29
申请号：US12821933
申请日：2010-06-23
申请人： Garrett M. Drapala , Michael A. Blake , Timothy C. Bronson , Lawrence D. Curley
发明人： Garrett M. Drapala , Michael A. Blake , Timothy C. Bronson , Lawrence D. Curley
IPC分类号： G06F9/30
CPC分类号： G06F9/526 , G06F2209/522
摘要： Serializing instructions in a multiprocessor system includes receiving a plurality of processor requests at a central point in the multiprocessor system. Each of the plurality of processor requests includes a needs register having a requestor needs switch and a resource needs switch. The method also includes establishing a tail switch indicating the presence of the plurality of processor requests at the central point, establishing a sequential order of the plurality of processor requests, and processing the plurality of processor requests at the central point in the sequential order.
摘要翻译：在多处理器系统中串行化指令包括在多处理器系统的中心点处接收多个处理器请求。多个处理器请求中的每一个包括具有请求者需求切换和资源需要切换的需求寄存器。该方法还包括建立指示在中心点存在多个处理器请求的尾部开关，建立多个处理器请求的顺序，以及按照顺序在中心点处理多个处理器请求。

10. 发明授权

US06714826B1 Facility for simultaneously outputting both a mixed digital audio signal and an unmixed digital audio signal multiple concurrently received streams of digital audio data 有权
标题翻译：用于同时输出混合数字音频信号和未混合数字音频信号的设备，多个同时接收的数字音频数据流
公开(公告)号：US06714826B1
公开(公告)日：2004-03-30
申请号：US09524461
申请日：2000-03-13
申请人： Lawrence D. Curley , James F. Driftmyer , Eric M. Foster
发明人： Lawrence D. Curley , James F. Driftmyer , Eric M. Foster
IPC分类号： G06F1700
CPC分类号： H04H60/04
摘要： A processing facility is provided for simultaneously receiving multiple streams of digital audio data and based thereon concurrently outputting both an unmixed digital audio signal and a mixed digital audio signal. The processing facility can be implemented, for example, within an audio decoder of a set top box. The facility includes receiving a first stream of digital audio data and a second stream of digital audio data, and outputting the first stream of digital audio data as an unmixed digital audio signal. Simultaneous therewith, the first stream of digital audio data and the second stream of digital audio data are digitally mixed and outputted as a mixed digital audio signal. If necessary, the second stream of digital audio data is redigitized based on a sample frequency of the first stream of digital audio data, and either or both the first stream and second stream of digital audio data are decoded prior to mixing.
摘要翻译：提供了一种处理设备，用于同时接收多个数字音频数据流，并且基于此同时输出未混合的数字音频信号和混合的数字音频信号。处理设施可以例如在机顶盒的音频解码器内实现。该设施包括接收第一数字音频数据流和第二数字音频数据流，并输出第一数字音频数据流作为非混合数字音频信号。与此同时，第一数字音频数据流和第二数字音频数据流被数字混合并输出为混合数字音频信号。如果需要，基于第一数字音频数据流的采样频率来重新编码第二数字音频数据流，并且在混合之前对第一流和第二数字音频数据流进行解码。

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