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1. 发明专利

JP2006128703A Semiconductor device including multi-bit non-volatile memory cell and manufacture method therefor 有权
标题翻译：包含多位非易失性存储器单元的半导体器件及其制造方法
公开(公告)号：JP2006128703A
公开(公告)日：2006-05-18
申请号：JP2005315324
申请日：2005-10-28
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： SEO BO-YOUNG , JEON HEE-SEOG , KANG SUNG-TAEG
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5692 , G11C16/0458 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that includes a multi-bit non-volatile memory cell and its manufacture method.
SOLUTION: The non-volatile semiconductor device includes a unit cell, comprising a plurality of transistors the source and drain regions of which are shared, wherein each of the plurality of transistors includes at least one control gate and at least one charge accumulation region, and each control gate is connected to at least one control voltage for shifting the threshold voltage of each transistor. Due to this, it is possible to effectively increase the degree of integration and efficiently reduce the cost per megabyte of a flash EEPROM.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种包括多位非易失性存储单元的半导体器件及其制造方法。解决方案：非易失性半导体器件包括单元，其包括多个晶体管，源极和漏极区域共享，其中每个晶体管包括至少一个控制栅极和至少一个电荷积累区域，并且每个控制栅极连接至至少一个控制电压以移位每个晶体管的阈值电压。由此，可以有效地提高集成度并有效降低闪存EEPROM的每兆字节的成本。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2007142395A Nonvolatile memory element 有权
标题翻译：非易失性存储元件
公开(公告)号：JP2007142395A
公开(公告)日：2007-06-07
申请号：JP2006301714
申请日：2006-11-07
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： SEO BO-YOUNG , DEN KISHAKU , HAN JEONG-UK , KANG SUNG-TAEG
IPC分类号： H01L21/8247 , G11C16/02 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0408 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory element of improved integrity. SOLUTION: The nonvolatile memory element comprises memory cell units comprising a pair of memory transistors and one selective transistor. The selective transistor is arranged between the pair of the memory transistors formed in the active region in a semiconductor substrate. Two different bit lines are connected to a pair of memory transistors respectively. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种改进的完整性的非易失性存储元件。非易失性存储元件包括包括一对存储晶体管和一个选择晶体管的存储单元单元。选择晶体管布置在形成在半导体衬底中的有源区中的一对存储晶体管之间。两个不同的位线分别连接到一对存储器晶体管。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2014179155A Source line floating circuit, memory device including the same, and method for reading data in memory device 审中-公开
标题翻译：源极浮动电路，包括其的存储器件以及用于在存储器件中读取数据的方法
公开(公告)号：JP2014179155A
公开(公告)日：2014-09-25
申请号：JP2014043079
申请日：2014-03-05
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JEON CHANG-MIN , SEO BO-YOUNG , YOO TAE-KWANG
IPC分类号： G11C16/06 , G11C11/15 , G11C13/00
CPC分类号： G11C16/24 , G11C11/16 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C16/08 , G11C16/26 , G11C2213/79 , G11C2213/82
摘要： PROBLEM TO BE SOLVED: To provide a source line floating circuit, a memory device including the same, and a method for reading data in the memory device.SOLUTION: The memory device includes a memory cell array, a row selection circuit, and a source line floating circuit. Memory cells arranged in the memory cell array are coupled between source lines and bit lines and are selected per row by word lines. The row selection circuit generates a decoded row address signal on the basis of a row address signal and enables one selected word line among the word lines on the basis of the decoded row address signal. During a read operation, the source line floating circuit connects one selected source line coupled to the memory cells selected by the selected word line, out of the source lines to a ground voltage and disconnects unselected source lines except the selected source line from the ground voltage to float the unselected source lines.
摘要翻译：要解决的问题：提供一种源极线浮置电路，包括其的存储器件以及用于在存储器件中读取数据的方法。存储器件包括存储单元阵列，行选择电路和源极线路浮动电路。布置在存储单元阵列中的存储单元耦合在源极线和位线之间，并且每行按字线选择。行选择电路基于行地址信号生成解码行地址信号，并且基于解码的行地址信号使字线中的一个选定的字线成为可能。在读取操作期间，源极线浮置电路将耦合到由所选择的字线选择的存储器单元的一个选定源极线从源极线连接到地电压，并且将接地电压之外的所选择的源极线除去未选择的源极线浮动未选择的源代码行。

4. 发明专利

JP2006261668A Split gate type nonvolatile memory device and method for manufacturing the same 审中-公开
标题翻译：分离门型非易失性存储器件及其制造方法
公开(公告)号：JP2006261668A
公开(公告)日：2006-09-28
申请号：JP2006067961
申请日：2006-03-13
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JEON HEE-SEOG , KANG SUNG-TAEG , YOON SEUNG-BEOM , HAN JEONG-UK , KIN RYUTAI , SEO BO-YOUNG , KWON HYOK-KI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory device and a method for manufacturing the same.
SOLUTION: A split gate memory device of the present invention has a structure in which a floating gate coupling ratio has increased, and as a result, the efficiency and performance of programs and deletion operation are improved.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种非易失性存储装置及其制造方法。解决方案：本发明的分离栅极存储器件具有浮栅耦合比增加的结构，结果提高了程序的效率和性能以及删除操作。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2006253685A Split gate nonvolatile memory device and method of forming the same 审中-公开
标题翻译：分离栅非易失性存储器件及其形成方法
公开(公告)号：JP2006253685A
公开(公告)日：2006-09-21
申请号：JP2006061485
申请日：2006-03-07
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JEON HEE-SEOG , KANG SUNG-TAEG , YOON SEUNG-BEOM , HAN JEONG-UK , CHOI YONG-SUK , SEO BO-YOUNG , KWON HYOK-KI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7887 , H01L29/66825
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory device having a structure that improves efficiency of programming and erasing and improves performance, and provides an increased floating gate coupling ratio.
SOLUTION: A split gate memory cell structure is provided for a nonvolatile memory. The split gate memory cell includes first and second diffusion regions formed in a semiconductor substrate. A floating gate electrode is formed on a semiconductor substrate between the first and second diffusion regions, and the first side of the floating gate electrode is overlapped with a part of the first diffusion region. A control gate electrode is formed on the semiconductor substrate between the second side of the floating gate electrode and the second diffusion region. A tunnel insulating film is provided between the control gate electrode and the second side of the floating gate electrode. A coupling gate electrode is formed adjacently to the first side of the floating gate electrode on the first diffusion region in the semiconductor substrate. A coupling insulating film is provided between the coupling gate electrode and the first side of the floating gate electrode. Thickness of the coupling insulating film is small compared with the tunnel insulating film.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有提高编程和擦除效率并提高性能的结构的非易失性存储器件，并提供增加的浮栅耦合比。解决方案：为非易失性存储器提供分离栅极存储单元结构。分离栅极存储单元包括形成在半导体衬底中的第一和第二扩散区。在第一和第二扩散区之间的半导体衬底上形成浮栅电极，并且浮置栅电极的第一侧与第一扩散区的一部分重叠。控制栅电极形成在半导体衬底上，在浮置栅电极的第二侧和第二扩散区之间。隧道绝缘膜设置在控制栅电极和浮栅电极的第二侧之间。耦合栅电极形成在半导体衬底中的第一扩散区上的浮置栅电极的第一侧。耦合绝缘膜设置在耦合栅电极和浮栅电极的第一侧之间。耦合绝缘膜的厚度与隧道绝缘膜相比较小。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2008077826A Nonvolatile storage device and its operating method 审中-公开
标题翻译：非易失存储器件及其操作方法
公开(公告)号：JP2008077826A
公开(公告)日：2008-04-03
申请号：JP2007245909
申请日：2007-09-21
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： ZEN SHOBIN , JEON HEE-SEOG , YOO HYUN-KHE , SAI SEIKON , SEO BO-YOUNG , RYU SHIDO
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0433 , H01L27/115 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile storage device and its operating method. SOLUTION: The nonvolatile storage device includes a first transistor connected to an n-th bit line and a second transistor connected to a (n+1)th bit line. The first transistor and the second transistor are connected in series between the n-th bit line and the (n+1)th bit line. A nonvolatile storage device having two-transistor one-bit unit cells which are the same or similar in the structures of the source areas and drain areas of storage cells can be formed. The storage capacity of the storage device can be doubled since it has two-transistor 2-bit unit cells. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种非易失性存储装置及其操作方法。解决方案：非易失性存储装置包括连接到第n位线的第一晶体管和连接到第（n + 1）位线的第二晶体管。第一晶体管和第二晶体管串联连接在第n位线和第（n + 1）位线之间。可以形成具有在存储单元的源极区域和漏极区域的结构中相同或相似的双晶体管1位单元电池的非易失性存储器件。存储设备的存储容量可以翻倍，因为它具有双晶体管2位单位单元。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2007027766A Nonvolatile memory element having 3-transistor memory cell, and its manufacturing method 审中-公开
标题翻译：具有3晶体管存储单元的非易失性存储元件及其制造方法
公开(公告)号：JP2007027766A
公开(公告)日：2007-02-01
申请号：JP2006197343
申请日：2006-07-19
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JEON HEE-SEOG , HAN JEONG-UK , RHEE CHANG-HOUN , KANG SUNG-TAEG , SEO BO-YOUNG , KWON HYOK-KI
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11524 , G11C16/0433 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： PROBLEM TO BE SOLVED: To provide a 3-transistor nonvolatile memory cell. SOLUTION: The memory cell and its manufacturing method are characterized in that the cell is formed in a semiconductor substrate, and prepares source and drain regions separated from each other, source and drain selecting lines are provided on the semiconductor substrate between the source and drain regions, the source and drain selecting lines are adjacent to the source and drain regions, respectively, a cell gate pattern is formed between the source and drain selecting lines, a suspension impurity region is formed in a gap region lower portion between the selecting line and cell gate pattern, and a spacing between the cell gate pattern and selecting line is smaller than the width of the selecting line. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种3晶体管非易失性存储单元。解决方案：存储单元及其制造方法的特征在于，单元形成在半导体衬底中，并且准备彼此分离的源极和漏极区域，源极和漏极选择线设置在源极和源极之间的半导体衬底上和漏极区域，源极和漏极选择线分别与源极和漏极区相邻，在源极和漏极选择线之间形成单元栅极图案，在选择区域之间的间隙区域下部形成悬浮杂质区域线和单元栅极图案，单元栅极图案和选择线之间的间隔小于选择线的宽度。版权所有（C）2007，JPO＆INPIT

8. 发明专利

DE102004056090B4 Verfahren zur Herstellung eines Schichtaufbaus mit Dielektrikum und Halbleiterbauelement 未知
公开(公告)号：DE102004056090B4
公开(公告)日：2015-03-12
申请号：DE102004056090
申请日：2004-11-12
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KANG SUNG-TAEG , YOON SEUNG-BEOM , HAN JEONG-UK , SEO BO-YOUNG , PARK SUNG-WOO , PARK JI-HOON
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/314 , H01L27/115 , H01L29/788 , H01L29/792
摘要： Verfahren zur Herstellung eines Schichtaufbaus mit einer ersten leitfähigen Schicht (30), einer zweiten leitfähigen Schicht (66) und einer zwischenliegenden dielektrischen Schicht (60), mit der Schrittfolge: – Bereitstellen der ersten leitfähigen Schicht (30), – Durchführen einer ersten Wärmebehandlung (42) der ersten leitfähigen Schicht in einer Atmosphäre eines ersten Gases, das Silizium und Wasserstoff enthält, und eines zweiten Gases, das Stickstoff enthält, derart, dass die Oberflächenrauhigkeit einer Oberseite der ersten leitfähigen Schicht verringert wird, – Durchführen einer zweiten Wärmebehandlung (52) der ersten leitfähigen Schicht (30) in einer Atmosphäre eines dritten Gases, das Stickstoff enthält, derart, dass eine Oxinitrid-Grenzflächenschicht (54) direkt auf der Oberseite der ersten leitfähigen Schicht gebildet wird, – Aufbringen der dielektrischen Schicht (60) auf die Oxinitrid-Grenzflächenschicht (54) nach der zweiten Wärmebehandlung und – Aufbringen der zweiten leitfähigen Schicht (72) auf die dielektrische Schicht (60).

9. 发明专利

DE102006054967A1 Non-volatile-memory device for continuously saving data, has memory-cell unit has memory transistors and selection transistor that correspond to memory gates and selection gate, respectively 未知
公开(公告)号：DE102006054967A1
公开(公告)日：2007-07-05
申请号：DE102006054967
申请日：2006-11-16
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： SEO BO-YOUNG , JEON HEE-SEOG , HAN JEONG-UK , KANG SUNG-TAEG
IPC分类号： H01L27/115 , G11C16/04
摘要： A selection gate is formed on the active region of a substrate between first and second memory gates, which are formed between impurity-diffusion regions. A floating diffusion region is formed in the active region between the corresponding memory gate and the selection gate. A memory-cell unit (MC) has a primary memory transistor (MT1), a secondary memory transistor (MT2), and a selection transistor (ST) that correspond to the first memory gate, second memory gate, and selection gate, respectively.

10. 发明专利

DE102005052272A1 Nonvolatile semiconductor device e.g. electrically erasable programable ROM, has multi-bit nonvolatile memory unit cell with set of transistors for sharing source and drain regions 未知
公开(公告)号：DE102005052272A1
公开(公告)日：2006-06-01
申请号：DE102005052272
申请日：2005-10-27
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： SEO BO-YOUNG , JEON HEE-SEOG , KANG SUNG-TAEG
IPC分类号： H01L27/115 , G11C11/56 , H01L21/8247
摘要： The device has a multi-bit nonvolatile memory unit cell with a set of transistors (T1-Tn) for sharing source and drain regions. Each transistor includes a control gate and a charge storage region that accumulates charges within the transistors. The control gates are connected to a control voltage to shift a threshold voltage in the transistors to store multi-bit per unit cell. An independent claim is also included for a method of fabricating a nonvolatile semiconductor device.

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