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1. 发明专利

JP2011029586A Memory semiconductor device, method of manufacturing the same, and method of operating the same 有权
标题翻译：存储半导体器件，其制造方法及其操作方法
公开(公告)号：JP2011029586A
公开(公告)日：2011-02-10
申请号：JP2009285708
申请日：2009-12-16
申请人： Regents Of The Univ Of California , Samsung Electronics Co Ltd , ザリージェンツオブザユニバーシティオブカリフォルニアThe Regents of The University of California , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM JI-YOUNG , HAN JEONG-HEE , HONG AUGUSTIN JINWOO , PARK YONG-JIK , WANG KANG L
IPC分类号： H01L27/115 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a memory semiconductor device, a method of manufacturing the same, and a method of operating the same. SOLUTION: This memory semiconductor device can includes: a plurality of semiconductor patterns having a vertical long axis on the upper surface of a substrate and two-dimensionally arranged; and a plurality of word lines three-dimensionally arranged among the plurality of semiconductor patterns while having a long axis crossing the plurality of semiconductor patterns. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供一种存储半导体器件及其制造方法及其操作方法。解决方案：该存储半导体器件可以包括：在基板的上表面上具有垂直长轴的多个半导体图案，并且二维布置; 以及在多个半导体图案之间三维排列的多个字线，同时具有与多个半导体图案交叉的长轴。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2014170940A Semiconductor element and manufacturing method of the same 有权
标题翻译：半导体元件及其制造方法
公开(公告)号：JP2014170940A
公开(公告)日：2014-09-18
申请号：JP2014042126
申请日：2014-03-04
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM JI-YOUNG , KIM DAEIK , KIM GANG-WOOK , KIM NARA , LEE JAE-GOO , LEE KYU-HYUN , CHUNG HYUN WOO , JIN GYOYOUNG , HONG HYEONG-SUN , HWANG YOO-SANG
IPC分类号： H01L21/3205 , H01L21/02 , H01L21/768 , H01L21/822 , H01L21/8247 , H01L23/522 , H01L27/04 , H01L27/10 , H01L27/115
CPC分类号： H01L23/544 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L27/0688 , H01L27/10897 , H01L27/14632 , H01L27/14634 , H01L27/1464 , H01L2221/68327 , H01L2221/6835 , H01L2221/68363 , H01L2223/54426 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element and a manufacturing method of the same, which can achieve high integration by a simple process.SOLUTION: A semiconductor element manufacturing method according to the present invention comprises: providing a semiconductor substrate having a first surface and a second surface opposite to the first surface; forming an alignment key and a connection contact which are parallel with each other and separated from each other and extend to partially pierce the semiconductor substrate from the first surface toward the second surface; forming on the first surface of the semiconductor substrate, a first circuit electrically connected with the connection contact; recessing the second surface of the semiconductor substrate to form a third surface which exposes the alignment key and the connection contact; and forming on the third surface of the semiconductor substrate, a second circuit electrically connected with the connection contact.
摘要翻译：要解决的问题：提供一种可以通过简单的工艺实现高集成度的半导体元件及其制造方法。解决方案：根据本发明的半导体元件制造方法包括：提供具有第一表面的半导体衬底和与第一表面相对的第二表面; 形成彼此平行并且彼此分离并延伸以从所述第一表面朝向所述第二表面部分地刺穿所述半导体衬底的对准键和连接触点; 在所述半导体衬底的第一表面上形成与所述连接触点电连接的第一电路; 使半导体衬底的第二表面凹陷以形成暴露对准键和连接触点的第三表面; 以及在所述半导体衬底的第三表面上形成与所述连接触点电连接的第二电路。

3. 发明专利

JP2006211673A Multiplexer for soft switching without phase jump and multiplexing method 审中-公开
标题翻译：用于软切换的多路复用器，无相位跳变和多路复用方法
公开(公告)号：JP2006211673A
公开(公告)日：2006-08-10
申请号：JP2006018033
申请日：2006-01-26
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： SHIN JONG-SHIN , KIM JI-YOUNG , KWAK MYOUNG-BO , SEO IL-WON , KIM CHI-WON , KIM HYUN-GOO , PARK JAE-HYUN
IPC分类号： H03K17/693
CPC分类号： H03K17/693
摘要： PROBLEM TO BE SOLVED: To provide a multiplexer for soft switching without a phase jump, and a multiplexing method.
SOLUTION: The multiplexer comprises: a first inverter for inverting and outputting a first input signal; a second inverter for inverting and outputting a second input signal; a first transmission gate for transmitting the output signal of the first inverter to a common output terminal in response to a first control signal; a second transmission gate for transmitting the output signal of the second inverter to the common output terminal in response to a second control signal; and a third inverter for inverting and outputting a signal of the common output terminal, wherein the first control signal and the second control signal are non-overlapping signals which do not overlap with each other.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于没有相位跳变的软开关的多路复用器和多路复用方法。解决方案：多路复用器包括：第一反相器，用于反相并输出第一输入信号; 第二反相器，用于反相和输出第二输入信号; 第一传输门，用于响应于第一控制信号将第一反相器的输出信号发送到公共输出端; 第二传输门，用于响应于第二控制信号将第二反相器的输出信号发送到公共输出端; 以及第三反相器，用于反相和输出公共输出端子的信号，其中第一控制信号和第二控制信号是彼此不重叠的非重叠信号。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2008244486A Non-volatile memory element, manufacturing method thereof and semiconductor chip 审中-公开
标题翻译：非挥发性记忆元件及其制造方法及半导体芯片
公开(公告)号：JP2008244486A
公开(公告)日：2008-10-09
申请号：JP2008084147
申请日：2008-03-27
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： HAN JEONG-HEE , KIM JI-YOUNG , KIM CHUNG-WOO , WANG KANG LONG , MA SIGUANG
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L24/73 , H01L25/0657 , H01L25/18 , H01L29/66825 , H01L29/66833 , H01L29/7926 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2924/01019 , H01L2924/15311 , H01L2924/00014 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile memory element which can be easily and highly integrated and has high reliability, and to provide a manufacturing method thereof. SOLUTION: The non-volatile memory element has a first conductivity-type first doping layer 115 formed on a substrate 105; a second conductivity-type semiconductor column 120 extending upward to one surface of the substrate 105 from the first doping layer 115 and having a conductivity type reverse to the first conductivity type; a control gate electrode 150a surrounding the side wall of the semiconductor column 120; an electric charge storage layer 140a interposed between the semiconductor column 120 and the control gate electrode 150a; a first conductivity-type second doping layer 130 disposed on the semiconductor column 120 so as to be electrically coupled to the semiconductor column 120. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种易于高度集成并且具有高可靠性的非易失性存储元件，并提供其制造方法。解决方案：非易失性存储元件具有形成在衬底105上的第一导电型第一掺杂层115; 从第一掺杂层115向上延伸到衬底105的一个表面并具有与第一导电类型相反的导电类型的第二导电型半导体柱120; 围绕半导体柱120的侧壁的控制栅电极150a; 介于半导体柱120和控制栅电极150a之间的电荷存储层140a; 设置在半导体柱120上以便与半导体柱120电耦合的第一导电型第二掺杂层130.版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2008244485A Non-volatile memory element and manufacturing method thereof 审中-公开
标题翻译：非易失性存储元件及其制造方法
公开(公告)号：JP2008244485A
公开(公告)日：2008-10-09
申请号：JP2008083967
申请日：2008-03-27
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： HAN JEONG-HEE , KIM JI-YOUNG , WANG KANG LONG , KIM CHUNG-WOO , CHAE SOO-DOO , PARK CHAN-JIN
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/0688 , H01L27/11517 , H01L27/11551 , H01L27/11556 , H01L27/11568 , H01L27/11578 , H01L27/11582
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile memory element which can be easily and highly integrated and has high reliability, and a manufacturing method thereof.
SOLUTION: This non-volatile memory element has a plurality of first semiconductor layers, a plurality of second semiconductor layers, a plurality of first storage nodes and a plurality of first control gate electrodes. The first semiconductor layers are laminated on a substrate, the second semiconductor layers are interposed between the first semiconductor layers and recessed from one-side ends of the first semiconductor layers so as to limit a plurality of first trenches between the first semiconductor layers, the first storage nodes are provided on surfaces of the second semiconductor layers in the first trenches, and the first control gate electrodes are formed on the first storage nodes so as to fill the first trenches.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种易于高度集成并且具有高可靠性的非易失性存储元件及其制造方法。解决方案：该非易失性存储元件具有多个第一半导体层，多个第二半导体层，多个第一存储节点和多个第一控制栅电极。第一半导体层层叠在基板上，第二半导体层插入在第一半导体层之间并从第一半导体层的一侧端部凹入，以限制第一半导体层之间的多个第一沟槽，第一半导体层存储节点设置在第一沟槽中的第二半导体层的表面上，并且第一控制栅电极形成在第一存储节点上以便填充第一沟槽。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2007088418A Semiconductor element having lateral extended active region and its manufacturing method 有权
标题翻译：具有横向延伸活动区域的半导体元件及其制造方法
公开(公告)号：JP2007088418A
公开(公告)日：2007-04-05
申请号：JP2006133328
申请日：2006-05-12
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： CHO MIN-HEE , KIM JI-YOUNG
IPC分类号： H01L29/78 , H01L21/76 , H01L29/41 , H01L29/423 , H01L29/49
CPC分类号： H01L29/66621 , H01L21/823481 , H01L27/10876 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element having a lateral extended active region. SOLUTION: A semiconductor element has: an upper active region 53 provided in a substrate 51 and having a first width; a lower active region 67 connected with the lower part of the upper active region 53 and having a second width larger than the first width; an element isolation film 77 determining the upper and lower active regions in the substrate 51; and insulated gate electrodes 93E and 93S crossing the upper and lower active regions. The insulated gate electrodes 93E and 93S are extended into the lower active region 67 through the upper active region 53. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供具有横向延伸的有源区的半导体元件。解决方案：半导体元件具有：设置在基板51中并具有第一宽度的上部有源区域53; 下部有源区域67与上部有源区域53的下部连接并且具有大于第一宽度的第二宽度; 确定衬底51中的上和下活性区的元件隔离膜77; 以及与上下活性区域交叉的绝缘栅电极93E，93S。绝缘栅极电极93E和93S通过上部有源区域53延伸到下部有源区域67中。（C）2007，JPO＆INPIT

7. 发明专利

JP2012248841A Semiconductor device including double gate electrode structure, and manufacturing method for the same 审中-公开
标题翻译：包括双门电极结构的半导体器件及其制造方法
公开(公告)号：JP2012248841A
公开(公告)日：2012-12-13
申请号：JP2012118686
申请日：2012-05-24
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM JI-YOUNG , OH YONG-CHUL , WOO DONG-SOO , CHUNG HYUN WOO , JIN GYO-YOUNG , CHOI SEONG-KWAN , HONG HYEONG-SUN , HWANG YOO-SANG
IPC分类号： H01L21/336 , H01L21/8242 , H01L21/8244 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L27/108 , H01L27/11 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： G11C11/4096 , G11C11/404 , G11C11/4085 , H01L21/823437 , H01L27/10823 , H01L27/10873 , H01L27/10876 , H01L27/10891 , H01L27/10894 , H01L29/41741 , H01L29/4236 , H01L29/66484 , H01L29/66613 , H01L29/66666 , H01L29/7827 , H01L29/7831
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device including a double gate electrode structure, that can increase the on current while minimizing the generation of leakage current, and provide a manufacturing method for the semiconductor device.SOLUTION: A semiconductor device includes: a gate electrode disposed on a substrate; a first impurity implantation region and a second impurity implantation region disposed on the substrate so that each is disposed adjacent to each end of the gate electrode; and a channel region disposed between the first impurity implantation region and the second impurity implantation region. The gate electrode includes a first sub-gate electrode adjacent to the first impurity implantation region and a second sub-gate electrode adjacent to the second impurity implantation region. The first sub-gate electrode and the second sub-gate electrode are disposed on the channel region. In this semiconductor device, one channel region is independently controlled by the two sub-gates, so that the generation of leakage current can be minimized.
摘要翻译：解决的问题：提供一种包括双栅电极结构的半导体器件，其可以在使漏电流的产生最小化的同时增加导通电流，并提供半导体器件的制造方法。解决方案：半导体器件包括：设置在衬底上的栅电极; 设置在所述基板上的第一杂质注入区域和第二杂质注入区域，使得它们各自邻近所述栅极电极的每一端设置; 以及设置在第一杂质注入区和第二杂质注入区之间的沟道区。栅电极包括与第一杂质注入区相邻的第一子栅电极和与第二杂质注入区相邻的第二子栅电极。第一子栅极电极和第二子栅极电极设置在沟道区域上。在该半导体器件中，一个沟道区域由两个子栅极独立地控制，从而可以使泄漏电流的产生最小化。版权所有（C）2013，JPO＆INPIT

8. 发明专利

JP2008197109A Contamination analyzing apparatus, its method, and reticle washing system using it 有权
标题翻译：污染分析装置，其方法和使用它的垃圾洗涤系统
公开(公告)号：JP2008197109A
公开(公告)日：2008-08-28
申请号：JP2008034440
申请日：2008-02-15
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： LEE OK-SUN , CHOI HYUNG-SEOK , AHN YO-HAN , KIM JI-YOUNG
IPC分类号： G01N1/00 , G01N1/10 , G03F1/84
CPC分类号： G03F1/82 , G01N2015/0687
摘要： PROBLEM TO BE SOLVED: To provide an apparatus and method for analyzing contamination capable of improving the reliability of inspection when the contamination remaining on the inspection surface is analyzed after washing an inspecting object such as a reticle. SOLUTION: The apparatus for analyzing the contamination remaining on the inspection surface of the inspecting object comprises a sampling module for bringing the inspection surface of the inspecting object into contact with liquid and extracting sampling liquid, and an analyzer for analyzing the contaminant remaining on the inspection surface of the inspecting object from the sampling liquid. The sampling module comprises a liquid tank having a storage space capable of storing the inspection surface of the inspecting object, and a liquid supply nozzle for supplying the liquid to the storage space of the liquid tank. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于分析污染物的装置和方法，所述污染物在清洗诸如掩模版之类的检查对象之后分析在检查表面上残留的污染物时能够提高检查的可靠性。解决方案：用于分析检查对象的检查表面上残留的污染物的设备包括用于使检查对象的检查表面与液体接触并提取取样液的取样模块，以及用于分析剩余污染物的分析器在取样液体的检查对象的检查面上。采样模块包括具有能够存储检查对象的检查表面的存储空间的液体罐和用于将液体供应到液体箱的存储空间的液体供给喷嘴。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2006332651A Manufacturing method of semiconductor element 审中-公开
标题翻译：半导体元件的制造方法
公开(公告)号：JP2006332651A
公开(公告)日：2006-12-07
申请号：JP2006139276
申请日：2006-05-18
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KANG NAM JUNG , KIM JI-YOUNG
IPC分类号： H01L21/8242 , H01L21/28 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L27/108
CPC分类号： H01L21/823878 , H01L21/823814 , H01L27/10888 , H01L27/10894
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor element in which such a problem that: a source/drain domain profile is affected adversely by a thermal burden, is prevented; the method simplifies the steps for forming a photo-resist pattern for masking an ion implantation by reducing the number of the steps; and a fluctuation of transistor characteristics due to a plug effect is reduced. SOLUTION: This manufacturing method comprises: forming a gate electrode pattern on a semiconductor substrate 210 in which an activated domain is defined; disposing an interlayer insulating film thereon; etching a part of the interlayer insulating film positioned over the activated domain to form contact holes on the both sides of the gate electrode pattern according to a self lining-up method; and implantating ions through the contact holes to form a source/drain domain 240. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体元件的制造方法，其中出现以下问题：源/漏畴轮廓受到热负荷的不利影响; 该方法简化了通过减少步骤数来形成用于掩蔽离子注入的光致抗蚀剂图案的步骤; 并且由于插头效应引起的晶体管特性的波动减小。解决方案：该制造方法包括：在半导体衬底210上形成栅电极图案，其中定义了激活域; 在其上设置层间绝缘膜; 蚀刻位于激活畴上的层间绝缘膜的一部分，根据自排列方法在栅电极图案的两侧形成接触孔; 并且通过接触孔植入离子以形成源极/漏极域240。（C）2007，JPO和INPIT

10. 发明专利

JP2006136000A Spread spectrum clock generator and method for generating spread spectrum clock signal 有权
标题翻译：传播频谱时钟发生器和用于产生传播频谱时钟信号的方法
公开(公告)号：JP2006136000A
公开(公告)日：2006-05-25
申请号：JP2005323908
申请日：2005-11-08
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： SHIN JONG-SHIN , CHANG DUCK-HYUN , KIM JI-YOUNG , KWAK MYOUNG-BO , SEO IL-WON , KIM CHI-WON , KIM HYUN-GOO , PARK JAE-HYUN
IPC分类号： H03L7/22 , G06F1/04 , H03K7/06 , H03L7/087 , H03L7/18
CPC分类号： H03L7/18 , H03B23/00 , H03L7/0891
摘要： PROBLEM TO BE SOLVED: To provide a spread spectrum clock generator (SSCG) and a method for generating a spread spectrum clock (SSC) signal. SOLUTION: The SSCG may include a controller outputting a given modulation voltage signal on the basis of a difference between an average frequency of a first feedback signal and a comparison frequency signal inputted thereto, or on the basis of total phase variations between a second feedback signal and the comparison frequency signal, and a sub-system for generating a first control voltage as a function of an input reference frequency signal and a second feedback signal inputted thereto. An adder may add the first control voltage signal and the modulation voltage signal to generate a second control voltage signal, and a voltage control oscillator may generate the SSC signal on the basis of the second control voltage signal. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供扩频时钟发生器（SSCG）和用于产生扩频时钟（SSC）信号的方法。解决方案：SSCG可以包括：控制器，其基于第一反馈信号的平均频率和输入到其的比较频率信号之间的差异，或者基于第一反馈信号的输入的比较频率信号之间的总相位变化，输出给定的调制电压信号第二反馈信号和比较频率信号，以及用于产生作为输入的参考频率信号和输入的第二反馈信号的函数的第一控制电压的子系统。加法器可以添加第一控制电压信号和调制电压信号以产生第二控制电压信号，并且压控振荡器可以基于第二控制电压信号产生SSC信号。版权所有（C）2006，JPO＆NCIPI

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