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1. 发明专利

JP2014170940A Semiconductor element and manufacturing method of the same 有权
标题翻译：半导体元件及其制造方法
公开(公告)号：JP2014170940A
公开(公告)日：2014-09-18
申请号：JP2014042126
申请日：2014-03-04
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM JI-YOUNG , KIM DAEIK , KIM GANG-WOOK , KIM NARA , LEE JAE-GOO , LEE KYU-HYUN , CHUNG HYUN WOO , JIN GYOYOUNG , HONG HYEONG-SUN , HWANG YOO-SANG
IPC分类号： H01L21/3205 , H01L21/02 , H01L21/768 , H01L21/822 , H01L21/8247 , H01L23/522 , H01L27/04 , H01L27/10 , H01L27/115
CPC分类号： H01L23/544 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L27/0688 , H01L27/10897 , H01L27/14632 , H01L27/14634 , H01L27/1464 , H01L2221/68327 , H01L2221/6835 , H01L2221/68363 , H01L2223/54426 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element and a manufacturing method of the same, which can achieve high integration by a simple process.SOLUTION: A semiconductor element manufacturing method according to the present invention comprises: providing a semiconductor substrate having a first surface and a second surface opposite to the first surface; forming an alignment key and a connection contact which are parallel with each other and separated from each other and extend to partially pierce the semiconductor substrate from the first surface toward the second surface; forming on the first surface of the semiconductor substrate, a first circuit electrically connected with the connection contact; recessing the second surface of the semiconductor substrate to form a third surface which exposes the alignment key and the connection contact; and forming on the third surface of the semiconductor substrate, a second circuit electrically connected with the connection contact.
摘要翻译：要解决的问题：提供一种可以通过简单的工艺实现高集成度的半导体元件及其制造方法。解决方案：根据本发明的半导体元件制造方法包括：提供具有第一表面的半导体衬底和与第一表面相对的第二表面; 形成彼此平行并且彼此分离并延伸以从所述第一表面朝向所述第二表面部分地刺穿所述半导体衬底的对准键和连接触点; 在所述半导体衬底的第一表面上形成与所述连接触点电连接的第一电路; 使半导体衬底的第二表面凹陷以形成暴露对准键和连接触点的第三表面; 以及在所述半导体衬底的第三表面上形成与所述连接触点电连接的第二电路。

2. 发明专利

JP2012248841A Semiconductor device including double gate electrode structure, and manufacturing method for the same 审中-公开
标题翻译：包括双门电极结构的半导体器件及其制造方法
公开(公告)号：JP2012248841A
公开(公告)日：2012-12-13
申请号：JP2012118686
申请日：2012-05-24
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM JI-YOUNG , OH YONG-CHUL , WOO DONG-SOO , CHUNG HYUN WOO , JIN GYO-YOUNG , CHOI SEONG-KWAN , HONG HYEONG-SUN , HWANG YOO-SANG
IPC分类号： H01L21/336 , H01L21/8242 , H01L21/8244 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L27/108 , H01L27/11 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： G11C11/4096 , G11C11/404 , G11C11/4085 , H01L21/823437 , H01L27/10823 , H01L27/10873 , H01L27/10876 , H01L27/10891 , H01L27/10894 , H01L29/41741 , H01L29/4236 , H01L29/66484 , H01L29/66613 , H01L29/66666 , H01L29/7827 , H01L29/7831
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device including a double gate electrode structure, that can increase the on current while minimizing the generation of leakage current, and provide a manufacturing method for the semiconductor device.SOLUTION: A semiconductor device includes: a gate electrode disposed on a substrate; a first impurity implantation region and a second impurity implantation region disposed on the substrate so that each is disposed adjacent to each end of the gate electrode; and a channel region disposed between the first impurity implantation region and the second impurity implantation region. The gate electrode includes a first sub-gate electrode adjacent to the first impurity implantation region and a second sub-gate electrode adjacent to the second impurity implantation region. The first sub-gate electrode and the second sub-gate electrode are disposed on the channel region. In this semiconductor device, one channel region is independently controlled by the two sub-gates, so that the generation of leakage current can be minimized.
摘要翻译：解决的问题：提供一种包括双栅电极结构的半导体器件，其可以在使漏电流的产生最小化的同时增加导通电流，并提供半导体器件的制造方法。解决方案：半导体器件包括：设置在衬底上的栅电极; 设置在所述基板上的第一杂质注入区域和第二杂质注入区域，使得它们各自邻近所述栅极电极的每一端设置; 以及设置在第一杂质注入区和第二杂质注入区之间的沟道区。栅电极包括与第一杂质注入区相邻的第一子栅电极和与第二杂质注入区相邻的第二子栅电极。第一子栅极电极和第二子栅极电极设置在沟道区域上。在该半导体器件中，一个沟道区域由两个子栅极独立地控制，从而可以使泄漏电流的产生最小化。版权所有（C）2013，JPO＆INPIT

3. 发明专利

GB2399681B Method of manufacturing semiconductor device with contact body extending in direction of bit line to contact storage node 未知
公开(公告)号：GB2399681B
公开(公告)日：2005-06-22
申请号：GB0400866
申请日：2004-01-15
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： PARK JE-MIN , HWANG YOO-SANG
IPC分类号： H01L21/8242 , H01L21/60 , H01L27/02 , H01L27/108
摘要： A method of manufacturing a semiconductor device with contact bodies that extend in the direction of bit lines to contact storage nodes includes forming band-type openings by selectively etching an insulating layer that covers the bit lines. The band-type openings extend in a lengthwise direction of the gate lines to expose the first contact pads and have portions that protrude in a lengthwise direction of the bit lines. The method also includes forming a conductive layer on the insulating layer that fills the band-type openings and is electrically connected to the first contact pads. The conductive layer is then patterned to separate the conductive layer into individual storage node contact bodies that extend in a lengthwise direction of the bit lines. Storgage nodes are then formed on the storage node contact bodies.

4. 发明专利

DE102018111376A1 Integrierte Schaltungsvorrichtungen 未知
公开(公告)号：DE102018111376A1
公开(公告)日：2019-03-28
申请号：DE102018111376
申请日：2018-05-14
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： AHN JUN-HYEOK , KIM EUN-JUNG , KIM HUI-JUNG , LEE KI-SEOK , KIM BONG-SOO , LEE MYEONG-DONG , HAN SUNG-HEE , HWANG YOO-SANG
IPC分类号： H01L23/52 , H01L27/108
摘要： Eine integrierte Schaltungsvorrichtung (100A) kann ein Paar von Leitungsstrukturen (LT) umfassen. Jede Leitungsstruktur (LT) kann ein Paar von leitfähigen Leitungen (BL) umfassen, die sich in einer ersten horizontalen Richtung (Y) über ein Substrat (110) erstrecken, und ein Paar von isolierenden Abdeckmustern (136), die jeweils das Paar von leitfähigen Leitungen (BL) bedecken. Die integrierte Schaltungsvorrichtung (100A) kann einen leitfähigen Kontaktstopfen (199) zwischen dem Paar von Leitungsstrukturen (LT) umfassen, und einen Metallsilizidfilm (172), der eine Oberseite (199T) des leitfähigen Kontaktstopfens (199) zwischen dem Paar von isolierenden Abdeckmustern (136) kontaktiert. Der leitfähige Kontaktstopfen (199) kann eine erste Breite (W11) zwischen dem Paar von leitfähigen Leitungen (BL) aufweisen, und eine zweite Breite (W12) zwischen dem Paar von isolierenden Abdeckmustern (136) in einer zweiten horizontalen Richtung (X), die senkrecht ist zu der ersten horizontalen Richtung (Y), wobei die zweite Breite (W12) größer ist als die erste Breite (W11).

5. 发明专利

DE19930295C2 未知
公开(公告)号：DE19930295C2
公开(公告)日：2002-11-28
申请号：DE19930295
申请日：1999-07-01
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KWAK DONG-HWA , HWANG YOO-SANG , CHUNG TAE-YOUNG
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242
摘要： A semiconductor device and a method for making a semiconductor device having a pillar-shaped capacitor storage node compatible with a high dielectric film, wherein the pillar-shaped capacitor storage node includes a thick conductive metal layer that is easily etched and a thin conductive layer completely coating the thick conductive metal layer. The thin conductive layer protects the thick conductive metal layer during subsequent high dielectric deposition and annealing and various oxidation process.

6. 发明专利

DE102004002223B4 Verfahren zur Herstellung einer Halbleitervorrichtung 未知
公开(公告)号：DE102004002223B4
公开(公告)日：2011-01-13
申请号：DE102004002223
申请日：2004-01-15
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： PARK JE-MIN , HWANG YOO-SANG
IPC分类号： H01L21/8242 , H01L21/60 , H01L27/02 , H01L27/108

7. 发明专利

GB2399681A DRAM storage electrode contacts 未知
公开(公告)号：GB2399681A
公开(公告)日：2004-09-22
申请号：GB0400866
申请日：2004-01-15
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： PARK JE-MIN , HWANG YOO-SANG
IPC分类号： H01L21/8242 , H01L21/60 , H01L27/02 , H01L27/108
摘要： Zigzag shaped mask line patterns, aligned in the same direction as gate lines 200 and perpendicular to the bitlines 600, are used to etch contact hole openings exposing contact pads 410. Contact plugs are subsequently formed in the openings and storage electrodes are formed on the contact plugs. The invention facilitates reliable electrical connection between the device active regions and the storage electrodes.

8. 发明专利

DE102004002223A1 未知
公开(公告)号：DE102004002223A1
公开(公告)日：2004-08-05
申请号：DE102004002223
申请日：2004-01-15
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： PARK JE-MIN , HWANG YOO-SANG
IPC分类号： H01L21/8242 , H01L21/60 , H01L27/02 , H01L27/108
摘要： A method of manufacturing a semiconductor device with contact bodies that extend in the direction of bit lines to contact storage nodes includes forming band-type openings by selectively etching an insulating layer that covers the bit lines. The band-type openings extend in a lengthwise direction of the gate lines to expose the first contact pads and have portions that protrude in a lengthwise direction of the bit lines. The method also includes forming a conductive layer on the insulating layer that fills the band-type openings and is electrically connected to the first contact pads. The conductive layer is then patterned to separate the conductive layer into individual storage node contact bodies that extend in a lengthwise direction of the bit lines. Storgage nodes are then formed on the storage node contact bodies.

9. 发明专利

DE60041638D1 未知
公开(公告)号：DE60041638D1
公开(公告)日：2009-04-09
申请号：DE60041638
申请日：2000-12-08
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： PARK BYUNG-JUN , HWANG YOO-SANG
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L27/108
摘要： A method of forming a self-aligned contact structure in a semiconductor device, comprising: providing a semiconductor substrate having at least one active region; forming a first interlayer insulating layer on the semiconductor substrate; forming at least two parallel interconnections on the first interlayer insulating layer, each interconnection having sidewall, a bottom and a width (x); forming a second interlayer insulating layer having grooves exposing a top surface of the interconnections, respectively; isotropically etching the second interlayer insulating layer to increase a width of the exposed portion of each groove, the each groove having a top portion (z) and a bottom portion (y) over each interconnection; filing the grooves with a mask material; and forming a conductive layer pattern, the conductive layer pattern penetrating at least a portion of the first and second interlayer insulating layers between the interconnections, and being electrically connected to the at least one active region, whereby x‰¤y‰¤z and x

10. 发明专利

DE19930295A1 Columnar capacitor storage node useful in a DRAM 未知
公开(公告)号：DE19930295A1
公开(公告)日：2000-01-13
申请号：DE19930295
申请日：1999-07-01
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KWAK DONG-HWA , HWANG YOO-SANG , CHUNG TAE-YOUNG
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242
摘要： A capacitor storage node, comprising a thick easily etched conductive layer (110) and a thin protective conductive layer (114), is new. A capacitor storage node is formed by: (a) forming a contact plug (107) in an insulation layer (104) on a semiconductor substrate (100); (b) successively forming a first metal barrier layer (108), a first conductive layer (110) and a second metal barrier layer (112) on the insulation layer and on the plug; (c) applying a second thinner conductive layer (114); (d) etching the layers using a mask to form a multilayer columnar storage node electrically connected to the plug; (e) forming a metal spacer barrier layer (118a) on both side walls of the node; and (f) forming a conductive spacer layer (120a) on both side walls of the metal spacer barrier layer. Independent claims are also included for the following: (i) a similar process in which the metal barrier layers and the metal spacer barrier layer are omitted; and (ii) capacitor storage nodes produced by the above processes. Preferred Features: The metal barrier layers and the metal spacer barrier layer, or the first conductive layer used in process (i), consist of TiN, TiAlN, TiSiN, TaAlN, ruthenium oxide, iridium oxide, lanthanum-strontium-cobalt oxide or a conductive oxide of Ba, Sr and Ru.

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