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1. 发明专利

JP2009038378A Phase-change memory element equipped with schottky diode 审中-公开
标题翻译：相变存储元件配备肖特基二极管
公开(公告)号：JP2009038378A
公开(公告)日：2009-02-19
申请号：JP2008198204
申请日：2008-07-31
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： HA DAE-WON , JEONG GI-TAE
IPC分类号： H01L27/105 , H01L21/28 , H01L29/47 , H01L29/872 , H01L45/00
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To provide a phase-change memory element with low operating voltage and improved program efficiency.
SOLUTION: The phase-change memory element includes a word line extended in one direction on a substrate, a first semiconductor pattern disposed on the word line, a node electrode disposed on the first semiconductor pattern, a Schottky diode formed between the first semiconductor pattern and the node electrode, and a phase-change resistor disposed on the node electrode.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供具有低工作电压和提高的程序效率的相变存储元件。相变存储元件包括在基板上沿一个方向延伸的字线，设置在字线上的第一半导体图案，设置在第一半导体图案上的节点电极，形成在第一半导体图案之间的肖特基二极管半导体图案和节点电极，以及设置在节点电极上的相变电阻器。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2009020998A Multilevel phase change memory device to reduce read error, and readout method thereof 审中-公开
标题翻译：用于减少读取错误的多级相变存储器件及其读取方法
公开(公告)号：JP2009020998A
公开(公告)日：2009-01-29
申请号：JP2008180384
申请日：2008-07-10
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JEONG GI-TAE
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C2013/0054
摘要： PROBLEM TO BE SOLVED: To provide a phase change memory device and a reading method thereof. SOLUTION: This phase change memory device includes: a plurality of main cells programmed to have any one out of a plurality of resistance states corresponding to each of multi-bit data; a plurality of reference cells programmed to have at least two different resistance states among a plurality of the resistance states each time the main cells are programmed; and a reference voltage generation circuit which generates the reference voltage for sensing a plurality of reference cells, and identifying each of the plurality of the resistance states. The phase change memory device improves reliability of read operation while the resistance values of the phase change substance changes with time. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种相变存储器件及其读取方法。该相变存储器件包括：被编程为具有与多位数据中的每一个相对应的多个电阻状态中的任一个的多个主单元; 多个参考单元被编程为在每个主单元被编程时在多个电阻状态中具有至少两个不同的电阻状态; 以及参考电压产生电路，其生成用于感测多个参考单元的参考电压，并且识别多个电阻状态中的每一个。在相变物质的电阻值随时间变化的同时，相变存储器件提高读取操作的可靠性。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2006054046A Method of operating magnetic ram device using spin injection, and magnetic ram device 有权
标题翻译：使用旋转注射操作磁性RAM器件的方法和磁性RAM器件
公开(公告)号：JP2006054046A
公开(公告)日：2006-02-23
申请号：JP2005234722
申请日：2005-08-12
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JEONG WON-CHEOL , KIM KI-NAM , JEONG HONG-SIK , JEONG GI-TAE , PARK JAE-HYUN
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L29/82 , H01L43/08
CPC分类号： G11C11/16
摘要： PROBLEM TO BE SOLVED: To provide a method for operating a magnetic RAM device including a memory cell having a magnetic tunnel junction structure on a substrate. SOLUTION: The method is provided for operating the magnetic RAM device including the memory cell having the magnetic tunnel junction structures 41a, 41b on the substrate 1. The method includes steps of: impressing a writing current pulse through the magnetic tunnel junction structures 41a, 41b; and impressing a writing magnetic field pulse onto the magnetic tunnel junction structures, wherein at least a portion of the writing magnetic field pulse is overlapping in time with respect to at least a portion of the writing current pulse. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种在基板上操作包括具有磁性隧道结结构的存储单元的磁性RAM器件的方法。解决方案：提供了用于操作包括在衬底1上具有磁性隧道结结构41a，41b的存储单元的磁性RAM器件的方法。该方法包括以下步骤：通过磁性隧道结结构施加写入电流脉冲 41a，41b; 并将写入磁场脉冲施加到磁性隧道结结构上，其中写入磁场脉冲的至少一部分相对于写入电流脉冲的至少一部分在时间上重叠。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2009218598A Resistive memory device and method of forming the same 审中-公开
标题翻译：电阻记忆体装置及其形成方法
公开(公告)号：JP2009218598A
公开(公告)日：2009-09-24
申请号：JP2009056473
申请日：2009-03-10
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： RYOO KYUNG-CHANG , JEONG HONG-SIK , JEONG GI-TAE , KIM HYUNG-JUN , LIM DONG-WON
IPC分类号： H01L27/105 , H01L21/768 , H01L23/522 , H01L45/00
CPC分类号： H01L45/1675 , G11C11/5664 , G11C11/5678 , G11C13/0004 , G11C13/0014 , G11C13/0016 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683
摘要： PROBLEM TO BE SOLVED: To provide a phase change memory device that can be highly integrated and a method of forming the same. SOLUTION: Provided is a resistive memory device that can be highly integrated and the method of forming the same. An insulating layer 150 enclosing a resistive memory element 130 and an insulating layer 160 enclosing a conductive line 180 connected to the resistive memory element have different stresses, hardness, porosity degrees, dielectric constants or heat conductivities. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供可以高度集成的相变存储器件及其形成方法。解决方案：提供可以高度集成的电阻式存储器件及其形成方法。包围电阻性存储元件130的绝缘层150和封闭连接到电阻式存储元件的导线180的绝缘层160具有不同的应力，硬度，孔隙度，介电常数或热导率。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2009158098A Magnetic random access memory, its data sensing circuit, and its method 审中-公开
标题翻译：磁性随机存取存储器及其数据传感电路及其方法
公开(公告)号：JP2009158098A
公开(公告)日：2009-07-16
申请号：JP2009101370
申请日：2009-04-17
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JEONG GI-TAE
IPC分类号： G11C11/15 , G11C11/16
CPC分类号： G11C11/16 , G11C7/065 , G11C11/1673 , G11C13/004 , G11C27/024
摘要： PROBLEM TO BE SOLVED: To provide a magnetic random access memory MRAM capable of accurately determining data stored in a magnetic memory cell without using any reference cell. SOLUTION: The MRAM includes a memory cell array having magnetic memory cells arranged in lines and columns at intersection of word, bit and digit lines, and a sense amplifier for sensing data stored in a selected magnetic memory cell. The sense amplifier includes a current source for supplying one of first and second currents to the selected magnetic memory cell in response to a control signal, a first storage means for storing a first voltage in response to a first switching signal, a second storage means for storing a second voltage in response to a second switching signal, and a differential amplifier for determining data stored in the magnetic memory cell by using a difference between the first and second voltages. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够精确地确定存储在磁存储单元中的数据而不使用任何参考单元的磁随机存取存储器MRAM。解决方案：MRAM包括存储单元阵列，该存储单元阵列具有在字，位和数字线的相交处以线和列布置的磁存储单元，以及用于感测存储在所选择的磁存储单元中的数据的读出放大器。读出放大器包括用于响应于控制信号将第一和第二电流中的一个提供给所选磁存储单元的电流源，用于响应于第一开关信号存储第一电压的第一存储装置，用于存储响应于第二切换信号的第二电压;以及差分放大器，用于通过使用第一和第二电压之间的差来确定存储在磁存储单元中的数据。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2008276928A Multiple level cell phase change memory device having pre-read operation resistance drift recovery, memory system employing the same, and method for reading the memory device 审中-公开
标题翻译：具有预读操作电阻恢复的多级别单元更换存储器件，使用该存储器的存储器系统以及读取存储器件的方法
公开(公告)号：JP2008276928A
公开(公告)日：2008-11-13
申请号：JP2008119126
申请日：2008-04-30
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JEONG CHANG-WOOK , JEONG GI-TAE , KIM HYUNG-JUN , KO SEUNG-PIL
IPC分类号： G11C13/00
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0078 , Y10S977/754
摘要： PROBLEM TO BE SOLVED: To provide a method for reading a multiple level cell phase change memory device. SOLUTION: The memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于读取多级单元相变存储器件的方法。存储器件包括多个存储器单元，每个存储器单元包括存储单元材料，该存储单元材料具有响应于编程操作中应用的编程电流而确定的初始电阻，存储单元的电阻变化在编程操作之后的一段时间内从初始电阻开始，并且每个存储单元连接到存储器件的导线，该存储器单元用于在编程操作中应用编程电流来对相应的存储器单元的电阻进行编程，并且用于在读取操作中读取读取电流以读取相应的存储器单元的电阻。修改电路修改为读取操作选择的多个存储单元的存储单元的电阻，以在存储单元的读取操作之前将其电阻返回到接近初始电阻。版权所有（C）2009，JPO＆INPIT

7. 发明专利

DE102008021093A1 Memory i.e. multi-level phase change RAM, for use in e.g. laptop computer, has memory cells selected for read operation in order to restore resistance before read operation of memory cell in proximity of initial resistance 未知
公开(公告)号：DE102008021093A1
公开(公告)日：2008-11-06
申请号：DE102008021093
申请日：2008-04-28
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： JEONG CHANG-WOOK , JEONG GI-TAE , KIM HYEONG-JUN , KO SEUNG-PIL
IPC分类号： G11C13/02 , G11C16/34
摘要： The memory (200) has a modification circuit i.e. control logic (240) modifying resistance of a memory cell of multiple memory cells (210). The memory cells are selected for read operation in order to restore the resistance before the read operation of the memory cell in the proximity of initial resistance. The memory cells are programmed by a programming operation, and comprise a memory cell material e.g. calcogenide material. The memory cells are connected with a line of the memory. An independent claim is also included for a method for reading a memory.

8. 发明专利

DE102008032058B4 Mehrpegel-Phasenänderungsspeicher und verwandte Verfahren 未知
公开(公告)号：DE102008032058B4
公开(公告)日：2020-08-20
申请号：DE102008032058
申请日：2008-07-08
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： JEONG GI-TAE
IPC分类号： G11C13/02 , G11C11/56 , G11C16/00
摘要： Speicher (100; 410) mit variablem Widerstand, mit:einer Mehrzahl von Hauptzellen (MC -MC ), wobei jede der Mehrzahl von Hauptzellen auf einen von einer Mehrzahl von Widerstandszuständen (210, 220, 230, 240; 310, 320, 330, 340) programmiert ist, wobei die Widerstandszustände (210, 220, 230, 240; 310, 320, 330, 340) Mehr-Bit-Daten entsprechen;einer Mehrzahl von Bezugszellen (RMC , RMC ; RMC , RMC , RMC , RMC ), die auf mindestens zwei unterschiedliche Widerstandszustände der Widerstandszustände (210, 220, 230, 240; 310, 320, 330, 340) programmiert sind; undeiner Bezugsspannungs-Erzeugungsschaltung (140), die konfiguriert ist um die Bezugszellen (RMC , RMC ; RMC , RMC , RMC , RMC ) abzutasten und um Bezugsspannungen (Vref1, Vref2, Vref3) zum Identifizieren jedes der Widerstandszustände (210, 220, 230, 240; 310, 320, 330, 340) zu erzeugen,wobei der Speicher (100; 410) mit variablem Widerstand konfiguriert ist um die Bezugszellen (RMC , RMC ; RMC , RMC , RMC , RMC ) jedes Mal, wenn mindestens eine der Hauptzellen (MC -MC )programmiert wird, zu programmieren.

9. 发明专利

DE102008034007A1 未知
公开(公告)号：DE102008034007A1
公开(公告)日：2009-02-12
申请号：DE102008034007
申请日：2008-07-21
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： HA DAE-WON , JEONG GI-TAE
IPC分类号： H01L27/24 , H01L45/00
摘要： A phase change memory device includes wordlines extending along a direction on a semiconductor substrate. Low concentration semiconductor patterns are disposed on the wordlines. Node electrodes are disposed on the low concentration semiconductor patterns. Schottky diodes are disposed between the low concentration semiconductor patterns and the node electrodes. Phase change resistors are disposed on the node electrodes.

10. 发明专利

DE102008032058A1 未知
公开(公告)号：DE102008032058A1
公开(公告)日：2009-01-15
申请号：DE102008032058
申请日：2008-07-08
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： JEONG GI-TAE
IPC分类号： G11C13/02
摘要： Provided are a phase change memory device and a reading method thereof. An example embodiment of a phase change memory device may include main cells programmed to have any one of a plurality of resistance states respectively corresponding to multi-bit data, reference cells programmed to have at least two respectively different resistance states among the resistance states each time the main cells are programmed, and a reference voltage generation circuit sensing the reference cells to generate reference voltages for identifying each of the resistance states.

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