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1. 发明专利

JP2009038378A Phase-change memory element equipped with schottky diode 审中-公开
标题翻译：相变存储元件配备肖特基二极管
公开(公告)号：JP2009038378A
公开(公告)日：2009-02-19
申请号：JP2008198204
申请日：2008-07-31
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： HA DAE-WON , JEONG GI-TAE
IPC分类号： H01L27/105 , H01L21/28 , H01L29/47 , H01L29/872 , H01L45/00
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To provide a phase-change memory element with low operating voltage and improved program efficiency.
SOLUTION: The phase-change memory element includes a word line extended in one direction on a substrate, a first semiconductor pattern disposed on the word line, a node electrode disposed on the first semiconductor pattern, a Schottky diode formed between the first semiconductor pattern and the node electrode, and a phase-change resistor disposed on the node electrode.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供具有低工作电压和提高的程序效率的相变存储元件。相变存储元件包括在基板上沿一个方向延伸的字线，设置在字线上的第一半导体图案，设置在第一半导体图案上的节点电极，形成在第一半导体图案之间的肖特基二极管半导体图案和节点电极，以及设置在节点电极上的相变电阻器。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2009033177A Non-volatile memory elements including stacked nand-type resistive memory cell strings, and methods of manufacturing the same 有权
标题翻译：非易失性存储器元件，包括堆叠的NAND型电阻记忆体电池条，及其制造方法
公开(公告)号：JP2009033177A
公开(公告)日：2009-02-12
申请号：JP2008194064
申请日：2008-07-28
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KOH GWAN-HYEOB , HA DAE-WON
IPC分类号： H01L27/105 , G11C13/00 , H01L21/8246 , H01L27/10 , H01L45/00 , H01L49/00
CPC分类号： G11C13/003 , G11C11/1675 , G11C13/0004 , G11C13/0007 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/75 , H01L27/228 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/147
摘要： PROBLEM TO BE SOLVED: To provide non-volatile memory elements including stacked NAND-type resistive memory cell strings, and to provide methods of manufacturing the same. SOLUTION: The NAND-type resistive memory cell strings STR1 and STR2 include a bit line BL and a plurality of resistive memory cells CL1, CL2 and CL3 serially connected to the bit line BL. The plurality of resistive memory cells CL1, CL2 and CL3 respectively include a first node N1, a second node N2, a third node N3, heaters H1, H2 and H3 connected between the first node N1 and the second node N2, variable resistors R1, R2 and R3 connected between the second node N2 and the third node N3, and switching devices SW1, SW2 and SW3 having a first terminal connected to the first node N1 and a second terminal connected to the third node N3. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供包括堆叠的NAND型电阻式存储器单元串的非易失性存储元件，并提供其制造方法。解决方案：NAND型电阻存储单元串STR1和STR2包括一个位线BL和串联连接到位线BL的多个电阻存储单元CL1，CL2和CL3。多个电阻性存储单元CL1，CL2和CL3分别包括连接在第一节点N1和第二节点N2之间的第一节点N1，第二节点N2，第三节点N3，加热器H1，H2和H3，可变电阻器R1， R2和R3连接在第二节点N2和第三节点N3之间，以及具有连接到第一节点N1的第一终端的开关设备SW1，SW2和SW3以及连接到第三节点N3的第二终端。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2009071309A Multi-level memory devices and operation method therefor 有权
标题翻译：多级存储器件及其操作方法
公开(公告)号：JP2009071309A
公开(公告)日：2009-04-02
申请号：JP2008232710
申请日：2008-09-10
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KOH GWAN-HYEOB , HA DAE-WON
IPC分类号： H01L27/105 , G11C13/00 , H01L45/00
CPC分类号： G11C11/5678 , G11C11/56 , G11C13/0004
摘要： PROBLEM TO BE SOLVED: To provide a multi-level memory device having stable electrical characteristics, and to provide a method of operating it. SOLUTION: The device includes a memory structure arranged between a first electrode and a second electrode, and the distribution density of resistance levels in the memory structure around the minimum value of the resistance level is higher than that in the vicinity of the maximum value of the resistance level. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有稳定电特性的多级存储器件，并提供一种操作它的方法。解决方案：该装置包括布置在第一电极和第二电极之间的存储器结构，并且存储器结构中电阻水平的最小值周围的电阻电平的分布密度高于最大值附近的电阻值的分布密度电阻值的值。版权所有（C）2009，JPO＆INPIT

4. 发明专利

DE19835891A1 Semiconductor device, especially DRAM transistor production process 未知
公开(公告)号：DE19835891A1
公开(公告)日：1999-03-11
申请号：DE19835891
申请日：1998-08-07
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： HA DAE-WON
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/266
摘要： A transistor production process involves selective ion implantation in an active semiconductor substrate region for producing a first doped region for punch-through prevention and a channel region-forming second doped region for threshold voltage control. Production of a semiconductor device, especially a transistor, involves (a) selectively implanting ions in an active region of a semiconductor substrate to produce a source/drain region-forming first doped region for preventing punch-through and a channel region-forming second doped region for controlling the threshold voltage; and (b) successively forming a gate oxide layer and a gate electrode on the active region for forming the channel. An Independent claim is also included for production of a semiconductor device with improved transistor properties, in which the above step (a) is replaced by (a') selectively implanting ions in an active region of a semiconductor substrate for producing a channel region-forming first doped region for controlling the threshold voltage and a second region for preventing punch-through.

5. 发明专利

DE102008034003A1 未知
公开(公告)号：DE102008034003A1
公开(公告)日：2009-01-29
申请号：DE102008034003
申请日：2008-07-21
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KOH GWAN-HYEOB , HA DAE-WON
IPC分类号： G11C13/02
摘要： A non-volatile memory device includes a substrate, an insulating layer on the substrate, and a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality of resistive memory cells is on the first one of the plurality of resistive memory cells to define a NAND-type resistive memory cell string. A bit line on the insulating layer is electrically connected to a last one of the plurality of resistive memory cells. At least one of the plurality of resistive memory cells may include a switching device and a data storage element including a variable resistor connected in parallel with the switching device. Related devices and fabrication methods are also discussed.

6. 发明专利

DE102008045963A1 未知
公开(公告)号：DE102008045963A1
公开(公告)日：2009-03-12
申请号：DE102008045963
申请日：2008-09-05
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KOH GWAN-HYEOB , HA DAE-WON
IPC分类号： G11C13/00 , G11C13/02
摘要： The present invention provides a multi-level memory device and method of operating the same. The device comprises a memory structure in which a distribution density of resistance levels around its minimum value is higher than that around its maximum value.

7. 发明专利

DE102008034007A1 未知
公开(公告)号：DE102008034007A1
公开(公告)日：2009-02-12
申请号：DE102008034007
申请日：2008-07-21
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： HA DAE-WON , JEONG GI-TAE
IPC分类号： H01L27/24 , H01L45/00
摘要： A phase change memory device includes wordlines extending along a direction on a semiconductor substrate. Low concentration semiconductor patterns are disposed on the wordlines. Node electrodes are disposed on the low concentration semiconductor patterns. Schottky diodes are disposed between the low concentration semiconductor patterns and the node electrodes. Phase change resistors are disposed on the node electrodes.

8. 发明专利

DE19835891B4 未知
公开(公告)号：DE19835891B4
公开(公告)日：2004-01-29
申请号：DE19835891
申请日：1998-08-07
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： HA DAE-WON
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/266
摘要： Multiple implants are performed in an integrated circuit substrate by implanting ions into a face thereof. Then, a gate insulating layer and a gate electrode are formed on the face of the integrated circuit substrate after performing the multiple implants in the integrated circuit substrate. Preferably, ions are not implanted into the integrated circuit substrate through the face after forming the gate insulating layer and the gate electrode on the face of the integrated circuit substrate. By preferably performing all implants prior to forming a gate insulating layer, the gate insulating layer is not degraded by implanting ions into the face of the integrated circuit substrate through the gate insulating layer.

9. 发明专利

DE102008034003B4 Nichtflüchtige Speicher mit Ketten von gestapelten resistiven Speicherzellen eines NAND-Typs und Verfahren zum Fertigen derselben 未知
公开(公告)号：DE102008034003B4
公开(公告)日：2022-02-10
申请号：DE102008034003
申请日：2008-07-21
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KOH GWAN-HYEOB , HA DAE-WON
IPC分类号： G11C13/02 , G11C11/00 , G11C16/02 , H01L27/10
摘要： Nichtflüchtiger Speicher mit:einem Substrat (1);einer Isolierschicht (11, 15, 33, 45, 57; 11, 15, 111, 123, 135) an dem Substrat (1);einer Mehrzahl von in Reihe geschalteten resistiven Speicherzellen (CL1, CL2, CL3), die in der Isolierschicht (11, 15, 33, 45, 57; 11, 15, 111, 123, 135) gestapelt sind, derart, dass sich eine erste (CL1) der Mehrzahl von resistiven Speicherzellen (CL1, CL2, CL3) auf dem Substrat (1) befindet und sich eine nächste (CL2) der Mehrzahl von resistiven Speicherzellen (CL1, CL2, CL3) auf der ersten (CL1) der Mehrzahl von resistiven Speicherzellen (CL1, CL2, CL3) befindet, um eine Kette (STR1, STR2) von resistiven Speicherzellen eines NAND-Typs zu definieren; undeiner Bitleitung (61, 139), die sich an der Isolierschicht (11, 15, 33, 45, 57; 11, 15, 111, 123, 135) befindet und mit einer letzten (CL3) der Mehrzahl von resistiven Speicherzellen (CL1, CL2, CL3) elektrisch verbunden ist,wobei mindestens eine der Mehrzahl von resistiven Speicherzellen (CL1, CL2, CL3) folgende Merkmale aufweist:eine Schaltvorrichtung (SW1, SW2, SW3), die eine Körperstruktur (17b, 35b, 47b) mit einer Source-Region (17s, 35s, 47s), einer Kanalregion (17c, 35c, 47c) und einer Drain-Region (17d, 35d, 47d), die in der Isolierschicht (11, 15, 33, 45, 57; 11, 15, 111, 123, 135) gestapelt sind, und eine Gate-Elektrode (23, 37, 49) an einer Seitenwand der Körperstruktur (17b, 35b, 47b) aufweist; undein Datenspeicherelement, das parallel zu der Schaltvorrichtung (SW1, SW2, SW3) geschaltet ist, wobei das Datenspeicherelement folgende Merkmale aufweist:eine untere Elektrode (27, 39, 51; 103, 115, 127), die von der Körperstruktur (17b, 35b, 47b) der Schaltvorrichtung (SW1, SW2, SW3) beabstandet ist;einen variablen Widerstand (29, 41, 53; 107, 119, 131) an der unteren Elektrode (27, 39, 51; 103, 115, 127); undeine obere Elektrode (31, 43, 55; 109, 121, 133) an dem variablen Widerstand (29, 41, 53; 107, 119, 131),wobei sich die obere Elektrode (31; 109) der ersten (CL1) der Mehrzahl von resistiven Speicherzellen (CL1, CL2, CL3) an der unteren Elektrode (39; 115) und der Körperstruktur (35b) der nächsten (CL2) der Mehrzahl von resistiven Speicherzellen (CL1, CL2, CL3) in der Kette (STR1, STR2) von resistiven Speicherzellen eines NAND-Typs befindet.

10. 发明专利

JP2000036597A MANUFACTURE OF MOS TRANSISTOR 失效
公开(公告)号：JP2000036597A
公开(公告)日：2000-02-02
申请号：JP18959199
申请日：1999-07-02
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： CHO CHANG-HYUN , KO KANKYO , RI BIKO , HA DAE-WON
IPC分类号： H01L29/772 , H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/10 , H01L29/78 , H01L21/322
摘要： PROBLEM TO BE SOLVED: To isolate the lattice defect such as an expanded defect, etc., from a p-n junction region. SOLUTION: This MOS transistor contains the first conductive type well region 104a formed in a semiconductor substrate 100, the first precipitated region 106 formed in the first depth in the region 104a to control substrate defect by implanting the first non-conductive impurities, a gate electrode 108 formed on the well region 104a, the second conductive type source/drain region 114 formed in the second depth which is deeper than the first depth in the well region on both sides of the electrode 108, and the second precipitated region 116 formed in the above-mentioned region 114 to control substrate depth by implanting the second non-conductive impurities.

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