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1. 发明专利

JP2007226952A Three-level nonvolatile semiconductor memory device which reduces coupling noise between memory cells, and its driving method 有权
标题翻译：降低记忆细胞之间的耦合噪声的三级非线性半导体存储器件及其驱动方法
公开(公告)号：JP2007226952A
公开(公告)日：2007-09-06
申请号：JP2007036466
申请日：2007-02-16
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： PARK KI TAE , CHOI JUNG-DAL
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2216/14
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device having a high degree of integration and high reliability, and to provide its driving method. SOLUTION: A three-level nonvolatile semiconductor memory device which reduces coupling noise between memory cells and its driving method are disclosed. The nonvolatile semiconductor memory device of the present invention includes memory cells that can be controlled to three threshold voltage levels and a page buffer for controlling the memory cells, and has a higher degree of integration than does a two-level nonvolatile semiconductor memory device and higher reliability than does a four-level nonvolatile semiconductor memory device. In the nonvolatile semiconductor memory device, memory cells which are controlled to have a relatively small voltage difference in the second and third page program steps are arranged at the left and right sides of the first memory cell, which is programmed to the second threshold voltage group in the first page program step. Accordingly, the nonvolatile semiconductor memory device and the driving method of the present invention can reduce coupling noise between memory cells in a worst case condition. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供具有高集成度和高可靠性的非易失性半导体存储器件，并提供其驱动方法。公开了一种降低存储单元之间的耦合噪声及其驱动方法的三电平非易失性半导体存储器件。本发明的非易失性半导体存储器件包括可被控制到三个阈值电压电平的存储器单元和用于控制存储器单元的页缓冲器，并且具有比两级非易失性半导体存储器件更高的集成度和更高的集成度可靠性高于四级非易失性半导体存储器件。在非易失性半导体存储器件中，在第二存储单元和第三页编程步骤中被控制为具有相对小的电压差的存储单元被布置在第一存储单元的左侧和右侧，其被编程到第二阈值电压组在第一页程序步骤。因此，本发明的非易失性半导体存储器件和驱动方法可以在最坏情况下降低存储单元之间的耦合噪声。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2007042265A 3-level nonvolatile semiconductor memory device and method of driving the same 有权
标题翻译： 3级非线性半导体存储器件及其驱动方法
公开(公告)号：JP2007042265A
公开(公告)日：2007-02-15
申请号：JP2006204977
申请日：2006-07-27
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： PARK KI TAE , CHOI JUNG-DAL , JO SUNG-KYU
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/24
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory device improving an operational speed by relieving layout load. SOLUTION: The nonvolatile semiconductor memory device is equipped with: a memory array in which a first string having first memory cells and a second string having second memory cells are included, and also the first string is coupled to a predetermined first bit line and the second string is coupled to the predetermined second bit line; a page buffer coupled to the memory array through the first and second bit lines and driven so that a pair of data of first to third bits are mapped to threshold voltage levels of one set of first and second memory cells; and a row decoder for controlling a word line of selected memory cell of the memory array. Above one set of first and second memory cells is dispersedly arranged to the first string and the second string and controlled by the same word line. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过减轻布局负载来提高操作速度的非易失性存储器件。解决方案：非易失性半导体存储器件配备有：包括具有第一存储单元的第一串和具有第二存储单元的第二串的存储器阵列，并且第一串耦合到预定的第一位线并且所述第二串耦合到所述预定的第二位线; 页缓冲器，其通过第一和第二位线耦合到存储器阵列并被驱动，使得第一到第三位的一对数据被映射到一组第一和第二存储器单元的阈值电压电平; 以及用于控制存储器阵列的选定存储单元的字线的行解码器。上述一组第一和第二存储单元分散地布置到第一串和第二串并由相同的字线控制。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2013115436A Three-dimensional semiconductor device 有权
标题翻译：三维半导体器件
公开(公告)号：JP2013115436A
公开(公告)日：2013-06-10
申请号：JP2012257685
申请日：2012-11-26
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： PARK ZHEN ZE , PARK YOUNG-WOO , CHOI JUNG-DAL
IPC分类号： H01L27/105 , H01L21/8246 , H01L27/10 , H01L45/00 , H01L49/00
CPC分类号： H01L27/249 , H01L27/228 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148
摘要： PROBLEM TO BE SOLVED: To provide a high-density, high-speed three-dimensional (resistivity) semiconductor (memory) device having increased degree of integration with a minimum number of mask steps.SOLUTION: A three-dimensional semiconductor device includes: a substrate including a first impurity region and a second impurity region separated by a channel region; a bit line connected to the first impurity region; a vertical electrode connected to the second impurity region; a laminate of a horizontal electrodes disposed between the substrate and the bit line; and a selection line disposed between the laminate and the substrate. At this time, the plane shape and plane position of the selection line can be substantially the same as the plane shape and plane position of each of the horizontal electrodes.
摘要翻译：要解决的问题：提供具有增加的集成度与最少数量的掩模步骤的高密度，高速三维（电阻率）半导体（存储器）器件。解决方案：三维半导体器件包括：衬底，其包括由沟道区分离的第一杂质区和第二杂质区; 连接到第一杂质区的位线; 连接到第二杂质区的垂直电极; 设置在所述基板和所述位线之间的水平电极的层叠体; 以及设置在层压体和基板之间的选择线。此时，选择线的平面形状和平面位置可以与每个水平电极的平面形状和平面位置基本相同。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2009117874A Floating trap type non-volatile memory device 有权
标题翻译：浮动捕获类型非易失性存储器件
公开(公告)号：JP2009117874A
公开(公告)日：2009-05-28
申请号：JP2009039605
申请日：2009-02-23
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： LEE CHANG-HYUN , CHOI JUNG-DAL , YE BYONG-WO
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28282 , H01L27/1157 , H01L29/4234 , H01L29/513
摘要： PROBLEM TO BE SOLVED: To accurately perform an erase operation even when a tunneling insulating layer is thickened so as to reinforce a data holding function in a floating trap type memory device.
SOLUTION: The floating trap type non-volatile memory device includes a semiconductor substrate 10, a gate electrode 27 formed on the substrate, the tunneling insulating film 20 laminated between the substrate and the gate electrode, a charge storage layer 22, and a blocking insulating film. Intensity of an electric field applied to the tunneling insulating film is higher than that of the electric field applied to the blocking insulating film.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：即使当隧道绝缘层变厚以便在浮动陷阱型存储装置中增强数据保持功能时，也能够精确地执行擦除操作。解决方案：浮置阱型非易失性存储器件包括半导体衬底10，形成在衬底上的栅电极27，层压在衬底和栅电极之间的隧道绝缘膜20，电荷存储层22和封闭绝缘膜。施加到隧道绝缘膜的电场强度高于施加到阻挡绝缘膜的电场的强度。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2008103733A Non-volatile memory device and method for forming the same 有权
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：JP2008103733A
公开(公告)日：2008-05-01
申请号：JP2007273038
申请日：2007-10-19
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： CHOI JUNG-DAL , SEL JONG-SUN , KANG CHANG-SEOK
IPC分类号： H01L21/8247 , H01L21/768 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/823462 , H01L21/823456 , H01L21/823475 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/11546 , Y10S257/903
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile memory device and a method for forming the same. SOLUTION: The non-volatile memory device includes a substrate having a cell region, a low voltage region, and a high voltage region. An earth selecting transistor, a string selecting transistor, and a cell transistor are positioned in the cell region. The low voltage transistor is positioned in the low voltage region. The high voltage transistor is positioned in the high voltage region. A common source contact is positioned on a dopant region of the earth selecting transistor, and a first low voltage contact is positioned on a dopant of the low voltage transistor. A bit line contact is positioned on a dopant of the string selecting transistor, and a first high voltage contact is positioned on a dopant of the high voltage transistor. The bit line is positioned on the bit line contact. A first interlayer insulating film is positioned on the substrate and a second interlayer insulating film is positioned on the first interlayer insulating film. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种非易失性存储器件及其形成方法。解决方案：非易失性存储器件包括具有单元区域，低电压区域和高电压区域的衬底。选择晶体管，串选择晶体管和单元晶体管位于单元区域中。低压晶体管位于低电压区域。高压晶体管位于高电压区域。公共源触点位于接地选择晶体管的掺杂区域上，第一低电压触点位于低电压晶体管的掺杂剂上。位线接触位于串选择晶体管的掺杂剂上，第一高电压接触位于高电压晶体管的掺杂剂上。位线位于位线接点上。第一层间绝缘膜位于基板上，第二层间绝缘膜位于第一层间绝缘膜上。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2010118138A Programming method for nonvolatile memory device 有权
标题翻译：非易失性存储器件的编程方法
公开(公告)号：JP2010118138A
公开(公告)日：2010-05-27
申请号：JP2009259206
申请日：2009-11-12
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： LEE JAE DUK , JUNG SOON MOON , CHOI JUNG-DAL
IPC分类号： G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： PROBLEM TO BE SOLVED: To provide a programming method for a nonvolatile memory device. SOLUTION: The programming method for a nonvolatile memory device includes: a stage in which a channel of a memory cell selected by programmed data is floated; and a stage in which the word lines of the selected and non-selected memory cells are driven so as to cause gate-induced drain leakage between the selected memory cell and the non-selected memory cell. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于非易失性存储器件的编程方法。非易失性存储器件的编程方法包括：通过编程数据选择的存储单元的通道浮动的阶段; 以及其中驱动所选择的和未选择的存储单元的字线以在所选择的存储单元和未选择的存储单元之间引起栅极引起的漏极泄漏的阶段。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2008118144A Nonvolatile memory device and method of fabricating the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：JP2008118144A
公开(公告)日：2008-05-22
申请号：JP2007288752
申请日：2007-11-06
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JEON SANG-HUN , KANG CHANG-SEOK , CHOI JUNG-DAL , PARK JIN-TAEK , SOHN WOONG-HEE , JUNG WON-SEOK
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526 , H01L27/11568 , H01L29/518 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory device which can prevent the degradation of operating characteristics.
SOLUTION: The nonvolatile memory device includes a semiconductor substrate 100 including a cell region and a peripheral circuit region, a cell gate 130 on the cell region, and peripheral circuit gates 120L, 120H on the peripheral circuit region. The cell gate 130 includes a charge storage insulating layer 132 on the semiconductor substrate 100, a gate electrode 134 on the charge storage insulating layer 132, and a conductive layer 136 on the gate electrode 134. The peripheral circuit gates 120L, 120H include gate insulating layers 122L, 122H on the semiconductor substrate 100, semiconductor insulating layers 124L, 124H on the gate insulating layers 122L, 122H, ohmic layers 126L, 126H on the semiconductor insulating layers 124L, 124H and the conductive layers 128L, 128H on the ohmic layers 126L, 126H.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够防止操作特性劣化的非易失性存储装置。解决方案：非易失性存储器件包括包括单元区域和外围电路区域的半导体衬底100，单元区域上的单元栅极130以及外围电路区域上的外围电路门120L，120H。电池栅极130包括半导体衬底100上的电荷存储绝缘层132，电荷存储绝缘层132上的栅电极134和栅电极134上的导电层136。外围电路门120L，120H包括栅极绝缘半导体衬底100上的层122L，122H，栅极绝缘层122L，122H上的半导体绝缘层124L，124H，半导体绝缘层124L，124H上的欧姆层126L，126H以及欧姆层126L上的导电层128L，128H ，126H。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2008022009A Nonvolatile memory device, and method of manufacturing same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：JP2008022009A
公开(公告)日：2008-01-31
申请号：JP2007182659
申请日：2007-07-11
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： SEL JONG-SUN , CHOI JUNG-DAL , PARK YOUNG-WOO , PARK JIN-TAEK
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11519 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory device the characteristics of which have been improved. SOLUTION: The nonvolatile memory device includes a semiconductor substrate including an active region and first and second memory cell strings on the active region. The first memory cell string including a plurality of first word lines that cross the active region between a first ground selection line and a first string selection line and a first arrangement interval is provided between adjoining lines in the plurality of the first word lines. The second memory cell string includes a plurality of second word lines that cross the active region between a second ground selection line and a second string selection line and the same first arrangement interval is provided between adjoining lines in the plurality of the second word lines. The first ground selection line is between the second ground selection line and the plurality of the first word lines and the second ground selection line is between the first ground selection line and the plurality of the second word lines. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种改进了其特性的非易失性存储器件。解决方案：非易失性存储器件包括在有源区域上包括有源区和第一和第二存储单元串的半导体衬底。在多个第一字线中的相邻行之间设置有包括与第一接地选择线和第一串选择线之间的有源区域相交叉的多个第一字线的第一存储单元串和第一配置间隔。第二存储单元串包括跨越第二接地选择线和第二串选择线之间的有源区的多个第二字线，并且在多个第二字线中的相邻线之间提供相同的第一布置间隔。第一接地选择线位于第二接地选择线与多个第一字线之间，第二接地选择线位于第一接地选择线与多个第二字线之间。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2006295191A Nonvolatile memory device and manufacturing method therefor 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：JP2006295191A
公开(公告)日：2006-10-26
申请号：JP2006110178
申请日：2006-04-12
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： SHIN YUTETSU , CHOI JUNG-DAL
IPC分类号： H01L21/8247 , H01L21/76 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11568
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory device and its manufacturing method. SOLUTION: A semiconductor substrate has a cell region, a high voltage region, and a low voltage region, wherein a mask is used that exposes the cell region and part of a device isolation film of the high voltage region. If the mask is used, steps and others can be performed in parallel, the steps of implanting threshold voltage adjustment impurity ions into the cell region, implanting channels doping impurity ions into the device isolation film of the high voltage region, and removing a low voltage gate conductive film and a low voltage gate insulated film to the cell region. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种非易失性存储器件及其制造方法。解决方案：半导体衬底具有单元区域，高电压区域和低电压区域，其中使用暴露高电压区域的单元区域和器件隔离膜的一部分的掩模。如果使用掩模，可以并行地执行步骤和其他步骤，将阈值电压调整杂质离子注入到单元区域中的步骤，将杂质离子掺杂到高电压区域的器件隔离膜中并除去低电压栅极导电膜和低电压栅极绝缘膜到电池区域。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2008217971A Nonvolatile memory element operating method 审中-公开
标题翻译：非易失性存储元件操作方法
公开(公告)号：JP2008217971A
公开(公告)日：2008-09-18
申请号：JP2008048339
申请日：2008-02-28
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： SETSU KOSHU , PARK SANG-JIN , LEE SUNG-HUN , PARK SUNG-IL , KIM JONGSEOB , CHOI JUNG-DAL , SAI KIKAN , SIM JAE-SUNG , MOON SEUNG-HYUN
IPC分类号： G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/14
摘要： PROBLEM TO BE SOLVED: To provide a method of operating a charge trap flash (CTF: Charge Trap Flash) memory element. SOLUTION: In the operating method of erasing in a charge trap memory element, erasing is performed by applying composite pulses containing DC pulses and DC perturbation pulses in a charge trap memory element. COPYRIGHT: (C)2008,JPO&INPIT

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