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1. 发明授权

US08411782B2 Parallel generation and matching of a deskew channel 有权
标题翻译：并行生成和匹配的歪斜通道
公开(公告)号：US08411782B2
公开(公告)日：2013-04-02
申请号：US12511917
申请日：2009-07-29
申请人： Samir Parikh , William W. Walker , Nestor Tzartzanis
发明人： Samir Parikh , William W. Walker , Nestor Tzartzanis
IPC分类号： H04B7/02 , H04L1/02
CPC分类号： H04L25/14
摘要： In one embodiment, a method includes receiving input data bits at a collective data rate, the input data bits being grouped into a plurality of input data words, the input data bits of each of the input data words being received from n parallel input-data-bit streams, each of the n parallel input-data-bit streams having a stream data rate that is 1/n of the collective data rate, each of the input data words comprising n consecutive ones of the input data bits; selecting particular input data bits; and generating a k-bit deskew channel with the selected input data bits, the deskew channel comprising a number of frames, each of the frames comprising x input data bits from one or more input data words and one or more framing bits. In another embodiment, a method includes using such a deskew channel to determine relative delays between data channels and the deskew channel.
摘要翻译：在一个实施例中，一种方法包括以集体数据速率接收输入数据位，输入数据位被分组成多个输入数据字，每个输入数据字的输入数据位从n个并行输入数据每个n个并行输入数据比特流具有作为集合数据速率的1 / n的流数据速率，每个输入数据字包括n个连续的输入数据位; 选择特定输入数据位; 以及生成具有所选择的输入数据位的k位去偏移通道，所述歪斜通道包括多个帧，每个帧包括来自一个或多个输入数据字的x个输入数据位和一个或多个成帧位。在另一个实施例中，一种方法包括使用这种歪斜通道来确定数据通道和歪斜通道之间的相对延迟。

2. 发明申请

US20100086075A1 Parallel Generation and Matching of a Deskew Channel 有权
标题翻译：平行生成和匹配纠错通道
公开(公告)号：US20100086075A1
公开(公告)日：2010-04-08
申请号：US12511917
申请日：2009-07-29
申请人： Samir Parikh , William W. Walker , Nestor Tzartzanis
发明人： Samir Parikh , William W. Walker , Nestor Tzartzanis
IPC分类号： H04B7/02
CPC分类号： H04L25/14
摘要： In one embodiment, a method includes receiving input data bits at a collective data rate, the input data bits being grouped into a plurality of input data words, the input data bits of each of the input data words being received from n parallel input-data-bit streams, each of the n parallel input-data-bit streams having a stream data rate that is 1/n of the collective data rate, each of the input data words comprising n consecutive ones of the input data bits; selecting particular input data bits; and generating a k-bit deskew channel with the selected input data bits, the deskew channel comprising a number of frames, each of the frames comprising x input data bits from one or more input data words and one or more framing bits. In another embodiment, a method includes using such a deskew channel to determine relative delays between data channels and the deskew channel.
摘要翻译：在一个实施例中，一种方法包括以集体数据速率接收输入数据位，输入数据位被分组成多个输入数据字，每个输入数据字的输入数据位从n个并行输入数据每个n个并行输入数据比特流具有作为集合数据速率的1 / n的流数据速率，每个输入数据字包括n个连续的输入数据位; 选择特定输入数据位; 以及生成具有所选择的输入数据位的k位去偏移通道，所述歪斜通道包括多个帧，每个帧包括来自一个或多个输入数据字的x个输入数据位和一个或多个成帧位。在另一个实施例中，一种方法包括使用这种歪斜通道来确定数据通道和歪斜通道之间的相对延迟。

3. 发明申请

US20120023380A1 ALGORITHMIC MATCHING OF A DESKEW CHANNEL 有权
标题翻译： DESKEW频道的算法匹配
公开(公告)号：US20120023380A1
公开(公告)日：2012-01-26
申请号：US12840985
申请日：2010-07-21
申请人： Samir Parikh , Nikola Nedovic , William W. Walker
发明人： Samir Parikh , Nikola Nedovic , William W. Walker
IPC分类号： G06F11/07
CPC分类号： H04L25/14
摘要： In one embodiment, a method includes receiving input data bits over data channels; receiving deskew channel bits constituting frames that each comprise ones of the input data bits; determining frame boundaries; mapping each of the input data bits in each of the frames to one of the data channels; for each set of the frames, comparing the input data bits in the set with the input data bits in the corresponding input data words; determining relative delays among the data channels and the deskew channel; when non-zero delays are determined, rearranging the input data bits to reduce the delays; and when it is determined that one or more of the data channels have a delay of greater than a predetermined number of data-channel clock periods relative to a particular data channel, delaying input data bits in the particular data channel by an additional number of input data bits.
摘要翻译：在一个实施例中，一种方法包括：通过数据信道接收输入数据位; 接收构成每个包括所述输入数据位中的一个的帧的歪斜通道位; 确定帧边界; 将每个帧中的每个输入数据位映射到数据信道之一; 对于每组帧，将该组中的输入数据位与相应输入数据字中的输入数据位进行比较; 确定数据通道和歪斜通道之间的相对延迟; 当确定非零延迟时，重新排列输入数据位以减少延迟; 并且当确定一个或多个数据信道相对于特定数据信道具有大于预定数量的数据信道时钟周期的延迟时，通过附加数量的输入来延迟特定数据信道中的输入数据位数据位。

4. 发明授权

US08432995B2 Algorithmic matching of a deskew channel 有权
标题翻译：歪斜通道的算法匹配
公开(公告)号：US08432995B2
公开(公告)日：2013-04-30
申请号：US12840985
申请日：2010-07-21
申请人： Samir Parikh , Nikola Nedovic , William W. Walker
发明人： Samir Parikh , Nikola Nedovic , William W. Walker
IPC分类号： H04B7/02 , H04L1/02
CPC分类号： H04L25/14
摘要： In one embodiment, a method includes receiving input data bits over data channels; receiving deskew channel bits constituting frames that each comprise ones of the input data bits; determining frame boundaries; mapping each of the input data bits in each of the frames to one of the data channels; for each set of the frames, comparing the input data bits in the set with the input data bits in the corresponding input data words; determining relative delays among the data channels and the deskew channel; when non-zero delays are determined, rearranging the input data bits to reduce the delays; and when it is determined that one or more of the data channels have a delay of greater than a predetermined number of data-channel clock periods relative to a particular data channel, delaying input data bits in the particular data channel by an additional number of input data bits.
摘要翻译：在一个实施例中，一种方法包括：通过数据信道接收输入数据位; 接收构成每个包括所述输入数据位中的一个的帧的歪斜通道位; 确定帧边界; 将每个帧中的每个输入数据位映射到数据信道之一; 对于每组帧，将该组中的输入数据位与相应输入数据字中的输入数据位进行比较; 确定数据通道和歪斜通道之间的相对延迟; 当确定非零延迟时，重新排列输入数据位以减少延迟; 并且当确定一个或多个数据信道相对于特定数据信道具有大于预定数量的数据信道时钟周期的延迟时，通过附加数量的输入来延迟特定数据信道中的输入数据位数据位。

5. 发明授权

US08493149B2 Amplifier circuit with variable tuning precision 有权
标题翻译：具有可变调谐精度的放大器电路
公开(公告)号：US08493149B2
公开(公告)日：2013-07-23
申请号：US13218080
申请日：2011-08-25
申请人： Samir Parikh
发明人： Samir Parikh
IPC分类号： H03F3/45
CPC分类号： H03G1/0029 , H03F3/45197 , H03F2203/45488 , H03G1/0088
摘要： Systems and methods are provided for facilitating variable precision tuning of an amplifier circuit. In accordance with one aspect of the present disclosure, the system includes an amplifier having multiple tuning stages to set the gain of the amplifier to discrete gain levels. In particular embodiments, the tuning stages are connected in series and each of the tuning stages includes a resistor connected in parallel to a switch, which can be disengaged to cause the amplifier to set the gain to an adjacent gain level. In certain embodiments, the difference in gain between each adjacent one of the plurality of gain levels is more at higher gain levels than at lower gain levels.
摘要翻译：提供了用于促进放大器电路的可变精度调谐的系统和方法。根据本公开的一个方面，该系统包括具有多个调谐级的放大器，以将放大器的增益设置为离散增益电平。在特定实施例中，调谐级串联连接，并且每个调谐级包括与开关并联连接的电阻器，该开关可以被分离以使放大器将增益设置为相邻的增益电平。在某些实施例中，多个增益电平中的每个相邻的增益电平之间的增益差在更高的增益水平上比在较低增益电平下更高。

6. 发明授权

US09106461B2 Quarter-rate speculative decision feedback equalizer 有权
标题翻译：四分之一投机决策反馈均衡器
公开(公告)号：US09106461B2
公开(公告)日：2015-08-11
申请号：US13554763
申请日：2012-07-20
申请人： Samir Parikh
发明人： Samir Parikh
IPC分类号： H04L25/08 , H04L25/03
CPC分类号： H04L25/03057
摘要： According to an aspect of an embodiment of the present disclosure, a method of relaxing a timing constraint associated with reducing inter-symbol interference (ISI) of input data includes adding an ISI cancellation value to input data received at a first clock rate to generate first speculative data. The method further includes subtracting the ISI cancellation value from the input data to generate second speculative data. The method also includes sampling the first speculative data and the second speculative data at a second clock rate that is one-fourth of the first clock rate such that a timing constraint associated with performing the ISI reduction is relaxed.
摘要翻译：根据本公开的实施例的一个方面，放宽与减少输入数据的符号间干扰（ISI）相关联的定时约束的方法包括将ISI抵消值添加到以第一时钟速率接收的输入数据以产生第一投机资料。该方法还包括从输入数据中减去ISI抵消值以产生第二推测数据。该方法还包括以第一时钟速率的四分之一的第二时钟速率对第一推测数据和第二推测数据进行采样，使得与执行ISI降低相关联的定时约束被放宽。

7. 发明授权

US07940777B2 Loss-free packet networks 有权
标题翻译：无损分组网络
公开(公告)号：US07940777B2
公开(公告)日：2011-05-10
申请号：US12037631
申请日：2008-02-26
申请人： Rajiv Asati , Greg Thompson , Christopher Metz , Samir Parikh
发明人： Rajiv Asati , Greg Thompson , Christopher Metz , Samir Parikh
IPC分类号： H04L12/56
CPC分类号： H04L45/28 , H04L1/007 , H04L45/04 , H04L45/50
摘要： In one embodiment, a method can include: receiving a packet in a device; classifying the received packet as a first packet type or a second packet type; when the packet is the first packet type, forwarding the packet to a next hop; and when the packet is the second packet type: performing forward error correction (FEC) encoding on the packet to generate repair data, modifying the packet by adding a multi-protocol label switching (MPLS) header to indicate that the packet is to be forwarded on an FEC-protected label switched path (LSP), generating an additional MPLS packet carrying the repair data, and forwarding the modified packet and the additional packet to a next hop.
摘要翻译：在一个实施例中，一种方法可以包括：在设备中接收分组; 将接收的分组分类为第一分组类型或第二分组类型; 当分组是第一分组类型时，将分组转发到下一跳; 并且当分组是第二分组类型时：对分组执行前向纠错（FEC）编码以产生修复数据，通过添加多协议标签交换（MPLS）报头来指示分组将被转发来修改分组在FEC保护的标签交换路径（LSP）上，生成携带修复数据的附加MPLS分组，并将修改的分组和附加分组转发到下一跳。

8. 发明授权

US06361239B1 Bolt with expandable bushing for pivot attachment 失效
标题翻译：螺栓与可扩展衬套枢轴连接
公开(公告)号：US06361239B1
公开(公告)日：2002-03-26
申请号：US09458744
申请日：1999-12-10
申请人： Samir Parikh , Susan M. Lipski
发明人： Samir Parikh , Susan M. Lipski
IPC分类号： B25G328
CPC分类号： B60N2/682 , B62D27/065 , Y10S411/903 , Y10S411/914 , Y10T403/4966
摘要： A pivot assembly is provided for pivotally attaching a pivotable seat component to a fixed seat component. The fixed component includes first and second apertures, first and second outer surfaces and first and second inner surfaces adjacent the apertures, and the pivotable component includes at least one pivot hole therein. The pivot assembly includes a bolt having a head, a cylindrical portion and a threaded portion. A threaded nut is engageable with the threaded portion of the bolt. A generally cylindrical plastic bushing is fitted over the cylindrical portion of the bolt and includes a peripheral lip abutting the head of the bolt and a plurality of swageable flanges extending at least partially over the threaded portion of the bolt. The swageable flanges cooperate to form a generally cylindrical shape having an outside diameter which is smaller than the first aperture and the pivot hole for insertion therethrough and larger than the second aperture for swaging against the second inner surface as the nut and bolt are threadedly engaged.
摘要翻译：枢轴组件被设置为用于将可枢转地安装在可枢转的座椅部件到固定的座椅部件。固定部件包括第一和第二孔，第一和第二外表面以及邻近孔的第一和第二内表面，并且可枢转部件在其中包括至少一个枢轴孔。枢轴组件包括具有头部，圆柱形部分和螺纹部分的螺栓。螺纹螺母可与螺栓的螺纹部分接合。大致圆柱形的塑料衬套安装在螺栓的圆柱形部分上，并且包括邻接螺栓头部的周边唇缘和至少部分地延伸到螺栓的螺纹部分上方的多个可加热凸缘。可变形凸缘协作形成具有小于第一孔的外径的大致圆柱形形状和用于插入其中的枢轴孔，并且当螺母和螺栓螺纹接合时，第二孔用于与第二内表面成型。

9. 发明申请

US20130049868A1 AMPLIFIER CIRCUIT WITH VARIABLE TUNING PRECISION 有权
标题翻译：具有可变调谐精度的放大器电路
公开(公告)号：US20130049868A1
公开(公告)日：2013-02-28
申请号：US13218080
申请日：2011-08-25
申请人： Samir Parikh
发明人： Samir Parikh
IPC分类号： H03G3/30
CPC分类号： H03G1/0029 , H03F3/45197 , H03F2203/45488 , H03G1/0088
摘要： Systems and methods are provided for facilitating variable precision tuning of an amplifier circuit. In accordance with one aspect of the present disclosure, the system includes an amplifier having multiple tuning stages to set the gain of the amplifier to discrete gain levels. In particular embodiments, the tuning stages are connected in series and each of the tuning stages includes a resistor connected in parallel to a switch, which can be disengaged to cause the amplifier to set the gain to an adjacent gain level. In certain embodiments, the difference in gain between each adjacent one of the plurality of gain levels is more at higher gain levels than at lower gain levels.
摘要翻译：提供了用于促进放大器电路的可变精度调谐的系统和方法。根据本公开的一个方面，该系统包括具有多个调谐级的放大器，以将放大器的增益设置为离散增益电平。在特定实施例中，调谐级串联连接，并且每个调谐级包括与开关并联连接的电阻器，该开关可以被分离以使放大器将增益设置为相邻的增益电平。在某些实施例中，多个增益电平中的每个相邻的增益电平之间的增益差在更高的增益水平上比在较低增益电平下更高。

10. 发明申请

US20090213726A1 LOSS-FREE PACKET NETWORKS 有权
标题翻译：无损包裹网络
公开(公告)号：US20090213726A1
公开(公告)日：2009-08-27
申请号：US12037631
申请日：2008-02-26
申请人： Rajiv Asati , Greg Thompson , Christopher Metz , Samir Parikh
发明人： Rajiv Asati , Greg Thompson , Christopher Metz , Samir Parikh
IPC分类号： G01R31/08
CPC分类号： H04L45/28 , H04L1/007 , H04L45/04 , H04L45/50
摘要： In one embodiment, a method can include: receiving a packet in a device; classifying the received packet as a first packet type or a second packet type; when the packet is the first packet type, forwarding the packet to a next hop; and when the packet is the second packet type: performing forward error correction (FEC) encoding on the packet to generate repair data, modifying the packet by adding a multi-protocol label switching (MPLS) header to indicate that the packet is to be forwarded on an FEC-protected label switched path (LSP), generating an additional MPLS packet carrying the repair data, and forwarding the modified packet and the additional packet to a next hop.
摘要翻译：在一个实施例中，一种方法可以包括：在设备中接收分组; 将接收的分组分类为第一分组类型或第二分组类型; 当分组是第一分组类型时，将分组转发到下一跳; 并且当分组是第二分组类型时：在分组上执行前向纠错（FEC）编码以产生修复数据，通过添加多协议标签交换（MPLS）报头来指示分组将被转发来修改分组在FEC保护的标签交换路径（LSP）上，生成携带修复数据的附加MPLS分组，并将修改的分组和附加分组转发到下一跳。

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