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1. 发明授权

US08411782B2 Parallel generation and matching of a deskew channel 有权
标题翻译：并行生成和匹配的歪斜通道
公开(公告)号：US08411782B2
公开(公告)日：2013-04-02
申请号：US12511917
申请日：2009-07-29
申请人： Samir Parikh , William W. Walker , Nestor Tzartzanis
发明人： Samir Parikh , William W. Walker , Nestor Tzartzanis
IPC分类号： H04B7/02 , H04L1/02
CPC分类号： H04L25/14
摘要： In one embodiment, a method includes receiving input data bits at a collective data rate, the input data bits being grouped into a plurality of input data words, the input data bits of each of the input data words being received from n parallel input-data-bit streams, each of the n parallel input-data-bit streams having a stream data rate that is 1/n of the collective data rate, each of the input data words comprising n consecutive ones of the input data bits; selecting particular input data bits; and generating a k-bit deskew channel with the selected input data bits, the deskew channel comprising a number of frames, each of the frames comprising x input data bits from one or more input data words and one or more framing bits. In another embodiment, a method includes using such a deskew channel to determine relative delays between data channels and the deskew channel.
摘要翻译：在一个实施例中，一种方法包括以集体数据速率接收输入数据位，输入数据位被分组成多个输入数据字，每个输入数据字的输入数据位从n个并行输入数据每个n个并行输入数据比特流具有作为集合数据速率的1 / n的流数据速率，每个输入数据字包括n个连续的输入数据位; 选择特定输入数据位; 以及生成具有所选择的输入数据位的k位去偏移通道，所述歪斜通道包括多个帧，每个帧包括来自一个或多个输入数据字的x个输入数据位和一个或多个成帧位。在另一个实施例中，一种方法包括使用这种歪斜通道来确定数据通道和歪斜通道之间的相对延迟。

2. 发明申请

US20100085086A1 Digital Frequency Detector 审中-公开
标题翻译：数字频率检测器
公开(公告)号：US20100085086A1
公开(公告)日：2010-04-08
申请号：US12510211
申请日：2009-07-27
申请人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker
发明人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker
IPC分类号： H03B19/00
CPC分类号： H03L7/091 , H03L7/099 , H03L7/10 , H03L2207/06 , H04L7/033
摘要： In one embodiment, a method is described that includes receiving a first clock signal and a second clock signal; dividing the first clock signal by a value of n to generate a divided first clock signal; sampling the frequency detector the divided first clock signal with the second clock signal to generate a plurality of samples; generating a first adjustment signal if more than a predetermined number of consecutive samples in a set of consecutive samples have identical logical values; and generating a second adjustment signal if less than the predetermined number of consecutive samples in the set of consecutive samples have identical logical values.
摘要翻译：在一个实施例中，描述了一种包括接收第一时钟信号和第二时钟信号的方法; 将第一时钟信号除以n的值以产生分割的第一时钟信号; 对所述分频的第一时钟信号与所述第二时钟信号对所述频率检测器进行采样以产生多个采样; 如果一组连续样本中多于一个预定数量的连续样本具有相同的逻辑值，则产生第一调整信号; 以及如果小于所述连续样本集合中的预定数量的连续样本具有相同的逻辑值，则产生第二调整信号。

3. 发明授权

US07626425B2 High performance clock-powered logic 有权
标题翻译：高性能时钟供电逻辑
公开(公告)号：US07626425B2
公开(公告)日：2009-12-01
申请号：US11332852
申请日：2006-01-13
申请人： William C. Athas , Nestor Tzartzanis , Weihua Mao , Lena Peterson
发明人： William C. Athas , Nestor Tzartzanis , Weihua Mao , Lena Peterson
IPC分类号： H03K19/00
CPC分类号： H03K19/0019
摘要： High performance clock-powered logic runs at below supply levels and reduces the need for faster digital logic circuitry. In a preferred embodiment, a clocked buffer is used to drive the signal line. The receiving end of the line is connected to a jam latch, preferably followed by an n-latch, followed by the digital logic, and followed by a second n-latch. The first n-latch is eliminated in an alternate embodiment, preferably one that uses complementary data signals.
摘要翻译：高性能时钟供电逻辑运行在低于电源电平，并减少对更快数字逻辑电路的需求。在优选实施例中，使用时钟缓冲器来驱动信号线。线路的接收端连接到卡锁锁存器，优选地跟随n锁存器，随后是数字逻辑，随后是第二个n锁存器。在替代实施例中，优选地使用互补数据信号来消除第一个n锁存器。

4. 发明申请

US20100090733A1 Generating Multiple Clock Phases 有权
标题翻译：生成多个时钟相位
公开(公告)号：US20100090733A1
公开(公告)日：2010-04-15
申请号：US12511352
申请日：2009-07-29
申请人： H. Anders Kristensson , Nestor Tzartzanis , Nikola Nedovic , William W. Walker
发明人： H. Anders Kristensson , Nestor Tzartzanis , Nikola Nedovic , William W. Walker
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/099 , H03L7/0998 , H04L7/0025 , H04L7/0337
摘要： In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; a circuit output for outputting an output signal; a first multiplying mixer cell (MMC) comprising a first MMC input, a second MMC input, and a first MMC output; a second MMC comprising a third MMC input, a fourth MMC input, and a second MMC output. In an example embodiment, the first circuit input is connected to the first MMC input; the second circuit input is connected to the third MMC input; the third circuit input is connected to the second MMC input and the fourth MMC input; the first MMC output and the second MMC output are combined with each other to provide the circuit output; and the output signal, when present, represents an error signal that is proportional to a phase difference between a phase of the target phase signal and an average of the first and second phases.
摘要翻译：在一个实施例中，电路包括用于接收具有第一相位的第一参考信号的第一电路输入端; 用于接收具有第二相位的第二参考信号的第二电路输入; 用于接收目标相位信号的第三电路输入; 用于输出输出信号的电路输出; 包括第一MMC输入，第二MMC输入和第一MMC输出的第一乘法混频器单元（MMC）; 第二MMC，包括第三MMC输入，第四MMC输入和第二MMC输出。在示例性实施例中，第一电路输入连接到第一MMC输入; 第二个电路输入连接到第三个MMC输入端; 第三电路输入连接到第二MMC输入和第四MMC输入; 第一MMC输出和第二MMC输出相互组合以提供电路输出; 并且当存在时，输出信号表示与目标相位信号的相位与第一和第二相位的平均值之间的相位差成比例的误差信号。

5. 发明授权

US07405593B2 Systems and methods for transmitting signals across integrated circuit chips 有权
标题翻译：跨集成电路芯片传输信号的系统和方法
公开(公告)号：US07405593B2
公开(公告)日：2008-07-29
申请号：US11265550
申请日：2005-11-01
申请人： Nestor Tzartzanis , William W. Walker
发明人： Nestor Tzartzanis , William W. Walker
IPC分类号： H03K19/094
CPC分类号： H04L25/0282 , H03K3/356191 , H03K3/35625 , H04L25/0272 , H04L25/0294 , Y10T83/2037 , Y10T83/204
摘要： Disclosed are on-chip global electrical signaling systems and methods employing differential current-mode sensing having reduced delay and energy dissipation compared to conventional inverter repeaters. The present inventions can be used for point-to-point connections as well as N-to-1 connections.
摘要翻译：本发明公开了采用差分电流模式感测的片上全球电信令系统和方法，与传统的逆变器中继器相比具有降低的延迟和能量消耗。本发明可以用于点到点连接以及N到1连接。

6. 发明授权

US07005893B1 High-performance clock-powered logic 失效
标题翻译：高性能时钟供电逻辑
公开(公告)号：US07005893B1
公开(公告)日：2006-02-28
申请号：US10031672
申请日：2000-07-18
申请人： William C. Athas , Nestor Tzartzanis , Weihua Mao , Lena Peterson
发明人： William C. Athas , Nestor Tzartzanis , Weihua Mao , Lena Peterson
IPC分类号： H03K19/096
CPC分类号： H03K19/0019
摘要： High performance clock-powered logic runs at below supply levels and reduces the need for faster digital logic circuitry. In a preferred embodiment, a clocked buffer (101) is used to drive the signal line. The receiving end of the line is connected to a jam latch (123), preferably followed by an n-latch (125), followed by the digital logic (109), and followed by a second n-latch (127). The first n-latch is eliminated in an alternative embodiment, preferably one that uses complementary data signals.
摘要翻译：高性能时钟供电逻辑运行在低于电源电平，并减少对更快数字逻辑电路的需求。在优选实施例中，使用时钟缓冲器（101）来驱动信号线。线的接收端连接到卡锁闩锁（123），优选地跟随着n锁存器（125），随后是数字逻辑（109），随后是第二n锁存器（127）。在替代实施例中，优选地使用互补数据信号的第一个n锁存器被消除。

7. 发明授权

US08058914B2 Generating multiple clock phases 有权
标题翻译：生成多个时钟阶段
公开(公告)号：US08058914B2
公开(公告)日：2011-11-15
申请号：US12511352
申请日：2009-07-29
申请人： H. Anders Kristensson , Nestor Tzartzanis , Nikola Nedovic , William W. Walker
发明人： H. Anders Kristensson , Nestor Tzartzanis , Nikola Nedovic , William W. Walker
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/099 , H03L7/0998 , H04L7/0025 , H04L7/0337
摘要： In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; a circuit output for outputting an output signal; a first multiplying mixer cell (MMC) comprising a first MMC input, a second MMC input, and a first MMC output; a second MMC comprising a third MMC input, a fourth MMC input, and a second MMC output. In an example embodiment, the first circuit input is connected to the first MMC input; the second circuit input is connected to the third MMC input; the third circuit input is connected to the second MMC input and the fourth MMC input; the first MMC output and the second MMC output are combined with each other to provide the circuit output; and the output signal, when present, represents an error signal that is proportional to a phase difference between a phase of the target phase signal and an average of the first and second phases.
摘要翻译：在一个实施例中，电路包括用于接收具有第一相位的第一参考信号的第一电路输入端; 用于接收具有第二相位的第二参考信号的第二电路输入; 用于接收目标相位信号的第三电路输入; 用于输出输出信号的电路输出; 包括第一MMC输入，第二MMC输入和第一MMC输出的第一乘法混频器单元（MMC）; 第二MMC，包括第三MMC输入，第四MMC输入和第二MMC输出。在示例性实施例中，第一电路输入连接到第一MMC输入; 第二个电路输入连接到第三个MMC输入端; 第三电路输入连接到第二MMC输入和第四MMC输入; 第一MMC输出和第二MMC输出相互组合以提供电路输出; 并且当存在时，输出信号表示与目标相位信号的相位与第一和第二相位的平均值之间的相位差成比例的误差信号。

8. 发明申请

US20100086075A1 Parallel Generation and Matching of a Deskew Channel 有权
标题翻译：平行生成和匹配纠错通道
公开(公告)号：US20100086075A1
公开(公告)日：2010-04-08
申请号：US12511917
申请日：2009-07-29
申请人： Samir Parikh , William W. Walker , Nestor Tzartzanis
发明人： Samir Parikh , William W. Walker , Nestor Tzartzanis
IPC分类号： H04B7/02
CPC分类号： H04L25/14
摘要： In one embodiment, a method includes receiving input data bits at a collective data rate, the input data bits being grouped into a plurality of input data words, the input data bits of each of the input data words being received from n parallel input-data-bit streams, each of the n parallel input-data-bit streams having a stream data rate that is 1/n of the collective data rate, each of the input data words comprising n consecutive ones of the input data bits; selecting particular input data bits; and generating a k-bit deskew channel with the selected input data bits, the deskew channel comprising a number of frames, each of the frames comprising x input data bits from one or more input data words and one or more framing bits. In another embodiment, a method includes using such a deskew channel to determine relative delays between data channels and the deskew channel.
摘要翻译：在一个实施例中，一种方法包括以集体数据速率接收输入数据位，输入数据位被分组成多个输入数据字，每个输入数据字的输入数据位从n个并行输入数据每个n个并行输入数据比特流具有作为集合数据速率的1 / n的流数据速率，每个输入数据字包括n个连续的输入数据位; 选择特定输入数据位; 以及生成具有所选择的输入数据位的k位去偏移通道，所述歪斜通道包括多个帧，每个帧包括来自一个或多个输入数据字的x个输入数据位和一个或多个成帧位。在另一个实施例中，一种方法包括使用这种歪斜通道来确定数据通道和歪斜通道之间的相对延迟。

9. 发明授权

US07616070B2 Electronic oscillators having a plurality of phased outputs and such oscillators with phase-setting and phase-reversal capability 有权
标题翻译：具有多个相控输出的电子振荡器和具有相位设定和相位反转能力的这种振荡器
公开(公告)号：US07616070B2
公开(公告)日：2009-11-10
申请号：US11934998
申请日：2007-11-05
申请人： Nestor Tzartzanis , William W. Walker
发明人： Nestor Tzartzanis , William W. Walker
IPC分类号： H03B27/00
CPC分类号： H03K3/0315 , H03B27/00
摘要： Disclosed are multiphase oscillators comprising a plurality of delay stages serially coupled in a loop by a plurality of nodes, with the loop being folded to provide two concentric rings of delay stages with equal numbers of allocated nodes. A second plurality of negative-resistance elements are provided, each element having a first output coupled to a node on the first concentric ring and a second output coupled to a node on the second concentric ring. Each such output switches between first and second voltage levels, and provides a negative resistance to a signal coupled to it during at least a portion of the transition between voltage levels. The outputs of an element switch to opposite voltage levels. With this construction, a high-voltage pulse propagates around the loop of delay stages, with a low-voltage pulse propagating behind it. Also disclosed are circuits to control the direction of pulse propagation.
摘要翻译：公开了多相振荡器，其包括多个延迟级，多个延迟级由多个节点在环路中串联耦合，环路被折叠以提供具有相等数量的分配节点的延迟级的两个同心环。提供了第二多个负电阻元件，每个元件具有耦合到第一同心环上的节点的第一输出和耦合到第二同心环上的节点的第二输出。每个这样的输出在第一和第二电压电平之间切换，并且在电压电平之间的至少一部分转换期间向与其耦合的信号提供负电阻。元件的输出切换到相反的电压电平。利用这种结构，高压脉冲在延迟级的环路周围传播，低压脉冲在其后面传播。还公开了控制脉冲传播方向的电路。

10. 发明申请

US20050180224A1 Differential current-mode sensing methods and apparatuses for memories 失效
标题翻译：用于存储器的差分电流模式感测方法和装置
公开(公告)号：US20050180224A1
公开(公告)日：2005-08-18
申请号：US10779464
申请日：2004-02-13
申请人： Nestor Tzartzanis , William Walker
发明人： Nestor Tzartzanis , William Walker
IPC分类号： G11C11/419 , G11C5/00 , G11C7/06 , G11C11/41 , G11C11/412 , G11C11/413
CPC分类号： G11C7/062 , G11C11/412 , G11C11/413
摘要： Disclosed is a memory architecture where current sense amplifiers are used instead of voltage sense amplifiers, and where the memory cells normally disposed along a single bit line are divided between two half bit lines. Each half bit line is coupled to a respective input of the current sense amplifier. When one of the memory cells is selected for reading, it couples a current related to its stored data state to the half bit line that it is coupled to. During this operation, a reference current is generated on the other half bit line. Also disclosed are novel current sense amplifiers.
摘要翻译：公开了一种存储架构，其中使用电流检测放大器来代替电压检测放大器，并且其中通常沿着单个位线布置的存储器单元被划分为两个半位线之间。每个半位线耦合到电流检测放大器的相应输入端。当选择其中一个存储单元进行读取时，它将与其存储的数据状态相关的电流与其耦合的半位线耦合。在该操作期间，在另一半位线上产生参考电流。还公开了新颖的电流检测放大器。

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