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1. 发明申请

US20140067845A1 FACILITATING FIELD PROGRAMMABLE GATE ARRAY ACCELERATIONS OF DATABASE FUNCTIONS 有权
公开(公告)号：US20140067845A1
公开(公告)日：2014-03-06
申请号：US13599600
申请日：2012-08-30
申请人： Sameh Asaad , Bernard V. Brezzo , Donna N. Eng Dillenberger , Parijat Dube , Balakrishna Raghavendra Iyer , Hong Min , Bharat Sukhwani , Mathew S. Thoennes
发明人： Sameh Asaad , Bernard V. Brezzo , Donna N. Eng Dillenberger , Parijat Dube , Balakrishna Raghavendra Iyer , Hong Min , Bharat Sukhwani , Mathew S. Thoennes
IPC分类号： G06F17/30
CPC分类号： G06F17/30 , G06F17/30289 , G06F17/30442
摘要： Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array.

2. 发明授权

US08977637B2 Facilitating field programmable gate array accelerations of database functions 有权
标题翻译：促进现场可编程门阵列加速的数据库功能
公开(公告)号：US08977637B2
公开(公告)日：2015-03-10
申请号：US13599600
申请日：2012-08-30
申请人： Sameh Asaad , Bernard V. Brezzo , Donna N Eng Dillenberger , Parijat Dube , Balakrishna Raghavendra Iyer , Hong Min , Bharat Sukhwani , Mathew S. Thoennes
发明人： Sameh Asaad , Bernard V. Brezzo , Donna N Eng Dillenberger , Parijat Dube , Balakrishna Raghavendra Iyer , Hong Min , Bharat Sukhwani , Mathew S. Thoennes
IPC分类号： G06F17/30
CPC分类号： G06F17/30 , G06F17/30289 , G06F17/30442
摘要： Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array.
摘要翻译：促进数据库功能加速的方法和安排。并入现场可编程门阵列。现场可编程门阵列中至少包含一个查询控制块，通过现场可编程门阵列加速数据库管理系统的运行。加速包括采用至少一个查询控制块来执行查询而不重新配置现场可编程门阵列。

3. 发明授权

US08983992B2 Facilitating field programmable gate array accelerations of database functions 有权
公开(公告)号：US08983992B2
公开(公告)日：2015-03-17
申请号：US13616639
申请日：2012-09-14
申请人： Sameh Asaad , Bernard V. Brezzo , Donna N Eng Dillenberger , Parijat Dube , Balakrishna Raghavendra Iyer , Hong Min , Bharat Sukhwani , Mathew S. Thoennes
发明人： Sameh Asaad , Bernard V. Brezzo , Donna N Eng Dillenberger , Parijat Dube , Balakrishna Raghavendra Iyer , Hong Min , Bharat Sukhwani , Mathew S. Thoennes
IPC分类号： G06F17/30
CPC分类号： G06F17/30 , G06F17/30289 , G06F17/30442
摘要： Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array.

4. 发明申请

US20140067851A1 FACILITATING FIELD PROGRAMMABLE GATE ARRAY ACCELERATIONS OF DATABASE FUNCTIONS 审中-公开
标题翻译：促进现场可编程序列阵列数据库功能的加速
公开(公告)号：US20140067851A1
公开(公告)日：2014-03-06
申请号：US13616639
申请日：2012-09-14
申请人： Sameh Asaad , Bernard V. Brezzo , Donna N. Eng Dillenberger , Parijat Dube , Balakrishna Raghavendra Iyer , Hong Min , Bharat Sukhwani , Mathew S. Thoennes
发明人： Sameh Asaad , Bernard V. Brezzo , Donna N. Eng Dillenberger , Parijat Dube , Balakrishna Raghavendra Iyer , Hong Min , Bharat Sukhwani , Mathew S. Thoennes
IPC分类号： G06F17/30
CPC分类号： G06F17/30 , G06F17/30289 , G06F17/30442
摘要： Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array.
摘要翻译：促进数据库功能加速的方法和安排。并入现场可编程门阵列。现场可编程门阵列中至少包含一个查询控制块，通过现场可编程门阵列加速数据库管理系统的运行。加速包括采用至少一个查询控制块来执行查询而不重新配置现场可编程门阵列。

5. 发明授权

US08838577B2 Accelerated row decompression 有权
标题翻译：加速行解压缩
公开(公告)号：US08838577B2
公开(公告)日：2014-09-16
申请号：US13556648
申请日：2012-07-24
申请人： Bharat Sukhwani , Sameh Asaad , Balakrishna Raghavendra Iyer , Hong Min , Mathew S. Thoennes
发明人： Bharat Sukhwani , Sameh Asaad , Balakrishna Raghavendra Iyer , Hong Min , Mathew S. Thoennes
IPC分类号： G06F7/00
CPC分类号： G06F17/30292 , G06F17/30286 , H03M7/3088
摘要： An apparatus comprises a hardware accelerator coupled to a memory. The hardware accelerator comprises one or more decompression units. The one or more decompression units are reconfigurable. The hardware accelerator may be a field-programmable gate array. The hardware accelerator may also comprise one or more reconfigurable scanner units. The one or more decompression units, in the aggregate, are operative to decompress one or more rows of a database at a bus speed of the coupling between the hardware accelerator and the memory. Two or more decompression units are operative to decompress two or more rows of a database in parallel. The apparatus allows for hardware accelerated row decompression.
摘要翻译：一种装置包括耦合到存储器的硬件加速器。硬件加速器包括一个或多个减压单元。一个或多个减压单元是可重新配置的。硬件加速器可以是现场可编程门阵列。硬件加速器还可以包括一个或多个可重新配置的扫描器单元。总的来说，一个或多个解压缩单元用于以硬件加速器和存储器之间的耦合的总线速度对数据库的一行或多行进行解压缩。两个或更多个解压缩单元用于并行地解压缩数据库的两行或更多行。该设备允许硬件加速行解压缩。

6. 发明申请

US20140032516A1 ACCELERATED ROW DECOMPRESSION 有权
标题翻译：加速方式解压缩
公开(公告)号：US20140032516A1
公开(公告)日：2014-01-30
申请号：US13556648
申请日：2012-07-24
申请人： Bharat Sukhwani , Sameh Asaad , Balakrishna R. Iyer , Hong Min , Mathew S. Thoennes
发明人： Bharat Sukhwani , Sameh Asaad , Balakrishna R. Iyer , Hong Min , Mathew S. Thoennes
IPC分类号： G06F17/30
CPC分类号： G06F17/30292 , G06F17/30286 , H03M7/3088
摘要： An apparatus comprises a hardware accelerator coupled to a memory. The hardware accelerator comprises one or more decompression units. The one or more decompression units are reconfigurable. The hardware accelerator may be a field-programmable gate array. The hardware accelerator may also comprise one or more reconfigurable scanner units. The one or more decompression units, in the aggregate, are operative to decompress one or more rows of a database at a bus speed of the coupling between the hardware accelerator and the memory. Two or more decompression units are operative to decompress two or more rows of a database in parallel. The apparatus allows for hardware accelerated row decompression.
摘要翻译：一种装置包括耦合到存储器的硬件加速器。硬件加速器包括一个或多个减压单元。一个或多个减压单元是可重新配置的。硬件加速器可以是现场可编程门阵列。硬件加速器还可以包括一个或多个可重新配置的扫描器单元。总的来说，一个或多个解压缩单元用于以硬件加速器和存储器之间的耦合的总线速度对数据库的一行或多行进行解压缩。两个或更多个解压缩单元用于并行地解压缩数据库的两行或更多行。该设备允许硬件加速行解压缩。

7. 发明授权

US08805850B2 Hardware-accelerated relational joins 有权
标题翻译：硬件加速关系连接
公开(公告)号：US08805850B2
公开(公告)日：2014-08-12
申请号：US13478507
申请日：2012-05-23
申请人： Bharat Sukhwani , Sameh W. Asaad , Hong Min , Mathew S. Thoennes , Gong Su
发明人： Bharat Sukhwani , Sameh W. Asaad , Hong Min , Mathew S. Thoennes , Gong Su
IPC分类号： G06F17/30
CPC分类号： G06F17/30498
摘要： Techniques are provided for hardware-accelerated relational joins. A first table comprising one or more rows is processed through a hardware accelerator. At least one join column in at least one of the one or more rows of the first table is hashed to set at least one bit in at least one bit vector. A second table comprising one or more rows is processed through a hardware accelerator. At least one join column in at least one of the one or more rows of the second table is hashed to generate at least one hash value. At least one bit vector is probed using the at least one hash value. A joined row is constructed responsive to the probing step. The row-construction step is performed in the hardware accelerator.
摘要翻译：为硬件加速的关系连接提供了技术。通过硬件加速器处理包括一行或多行的第一表。在第一表的一行或多行中的至少一行中的至少一个连接列被散列以在至少一个位向量中设置至少一个位。通过硬件加速器处理包括一行或多行的第二表。第二表的一行或多行中的至少一行中的至少一个连接列被散列以生成至少一个散列值。使用至少一个哈希值来探测至少一个比特向量。响应于探测步骤构建连接的行。行结构步骤在硬件加速器中执行。

8. 发明申请

US20130318107A1 GENERATING DATA FEED SPECIFIC PARSER CIRCUITS 有权
标题翻译：生成数据馈送特定分配器电路
公开(公告)号：US20130318107A1
公开(公告)日：2013-11-28
申请号：US13479132
申请日：2012-05-23
申请人： Sameh Asaad , Roger Moussalli , Bharat Sukhwani
发明人： Sameh Asaad , Roger Moussalli , Bharat Sukhwani
IPC分类号： G06F17/30
CPC分类号： G06F17/30519 , G06F17/30516
摘要： Generating a data feed specific parser circuit is provided. An input of a number of bytes of feed data associated with a particular data feed that the data feed specific parser circuit is to process is received. A feed format specification file that describes a data format of the particular data feed is parsed to generate an internal data structure of the feed format specification file. A minimum number of parallel pipeline stages in the data feed specific parser circuit to process the number of bytes of feed data associated with the particular data is determined based on the generated internal data structure of the feed format specification file. Then, a description of the data feed specific parser circuit with the determined number of parallel pipeline stages is generated.
摘要翻译：提供了生成数据馈送特定解析器电路。接收与数据馈送特定分析器电路要处理的特定数据馈送相关联的馈送数据的字节数的输入。描述描述特定数据馈送的数据格式的馈送格式规范文件被解析以生成馈送格式规范文件的内部数据结构。基于生成的馈送格式指定文件的内部数据结构，确定数据馈送特定解析器电路中用于处理与特定数据相关联的馈送数据的字节数的最小数量的并行流水线级。然后，生成具有确定数量的并行流水线级的数据馈送特定分析器电路的描述。

9. 发明申请

US20130318067A1 HARDWARE-ACCELERATED RELATIONAL JOINS 有权
标题翻译：硬件加速关系
公开(公告)号：US20130318067A1
公开(公告)日：2013-11-28
申请号：US13478507
申请日：2012-05-23
申请人： Bharat Sukhwani , Sameh W. Asaad , Hong Min , Matthew S. Thoennes , Gong Su
发明人： Bharat Sukhwani , Sameh W. Asaad , Hong Min , Matthew S. Thoennes , Gong Su
IPC分类号： G06F17/30
CPC分类号： G06F17/30498
摘要： Techniques are provided for hardware-accelerated relational joins. A first table comprising one or more rows is processed through a hardware accelerator. At least one join column in at least one of the one or more rows of the first table is hashed to set at least one bit in at least one bit vector. A second table comprising one or more rows is processed through a hardware accelerator. At least one join column in at least one of the one or more rows of the second table is hashed to generate at least one hash value. At least one bit vector is probed using the at least one hash value. A joined row is constructed responsive to the probing step. The row-construction step is performed in the hardware accelerator.
摘要翻译：为硬件加速的关系连接提供了技术。通过硬件加速器处理包括一行或多行的第一表。在第一表的一行或多行中的至少一行中的至少一个连接列被散列以在至少一个位向量中设置至少一个位。通过硬件加速器处理包括一行或多行的第二表。第二表的一行或多行中的至少一行中的至少一个连接列被散列以生成至少一个散列值。使用至少一个哈希值来探测至少一个比特向量。响应于探测步骤构建连接的行。行结构步骤在硬件加速器中执行。

10. 发明授权

US08788512B2 Generating data feed specific parser circuits 有权
标题翻译：生成数据馈送特定解析器电路
公开(公告)号：US08788512B2
公开(公告)日：2014-07-22
申请号：US13479132
申请日：2012-05-23
申请人： Sameh W. Asaad , Roger Moussalli , Bharat Sukhwani
发明人： Sameh W. Asaad , Roger Moussalli , Bharat Sukhwani
IPC分类号： G06F17/30
CPC分类号： G06F17/30519 , G06F17/30516
摘要： Generating a data feed specific parser circuit is provided. An input of a number of bytes of feed data associated with a particular data feed that the data feed specific parser circuit is to process is received. A feed format specification file that describes a data format of the particular data feed is parsed to generate an internal data structure of the feed format specification file. A minimum number of parallel pipeline stages in the data feed specific parser circuit to process the number of bytes of feed data associated with the particular data is determined based on the generated internal data structure of the feed format specification file. Then, a description of the data feed specific parser circuit with the determined number of parallel pipeline stages is generated.
摘要翻译：提供了生成数据馈送特定解析器电路。接收与数据馈送特定分析器电路要处理的特定数据馈送相关联的馈送数据的字节数的输入。描述描述特定数据馈送的数据格式的馈送格式规范文件被解析以生成馈送格式规范文件的内部数据结构。基于生成的馈送格式指定文件的内部数据结构，确定数据馈送特定解析器电路中用于处理与特定数据相关联的馈送数据的字节数的最小数量的并行流水线级。然后，生成具有确定数量的并行流水线级的数据馈送特定分析器电路的描述。

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