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1. 发明授权

US08788512B2 Generating data feed specific parser circuits 有权
标题翻译：生成数据馈送特定解析器电路
公开(公告)号：US08788512B2
公开(公告)日：2014-07-22
申请号：US13479132
申请日：2012-05-23
申请人： Sameh W. Asaad , Roger Moussalli , Bharat Sukhwani
发明人： Sameh W. Asaad , Roger Moussalli , Bharat Sukhwani
IPC分类号： G06F17/30
CPC分类号： G06F17/30519 , G06F17/30516
摘要： Generating a data feed specific parser circuit is provided. An input of a number of bytes of feed data associated with a particular data feed that the data feed specific parser circuit is to process is received. A feed format specification file that describes a data format of the particular data feed is parsed to generate an internal data structure of the feed format specification file. A minimum number of parallel pipeline stages in the data feed specific parser circuit to process the number of bytes of feed data associated with the particular data is determined based on the generated internal data structure of the feed format specification file. Then, a description of the data feed specific parser circuit with the determined number of parallel pipeline stages is generated.
摘要翻译：提供了生成数据馈送特定解析器电路。接收与数据馈送特定分析器电路要处理的特定数据馈送相关联的馈送数据的字节数的输入。描述描述特定数据馈送的数据格式的馈送格式规范文件被解析以生成馈送格式规范文件的内部数据结构。基于生成的馈送格式指定文件的内部数据结构，确定数据馈送特定解析器电路中用于处理与特定数据相关联的馈送数据的字节数的最小数量的并行流水线级。然后，生成具有确定数量的并行流水线级的数据馈送特定分析器电路的描述。

2. 发明申请

US20130318107A1 GENERATING DATA FEED SPECIFIC PARSER CIRCUITS 有权
标题翻译：生成数据馈送特定分配器电路
公开(公告)号：US20130318107A1
公开(公告)日：2013-11-28
申请号：US13479132
申请日：2012-05-23
申请人： Sameh Asaad , Roger Moussalli , Bharat Sukhwani
发明人： Sameh Asaad , Roger Moussalli , Bharat Sukhwani
IPC分类号： G06F17/30
CPC分类号： G06F17/30519 , G06F17/30516
摘要： Generating a data feed specific parser circuit is provided. An input of a number of bytes of feed data associated with a particular data feed that the data feed specific parser circuit is to process is received. A feed format specification file that describes a data format of the particular data feed is parsed to generate an internal data structure of the feed format specification file. A minimum number of parallel pipeline stages in the data feed specific parser circuit to process the number of bytes of feed data associated with the particular data is determined based on the generated internal data structure of the feed format specification file. Then, a description of the data feed specific parser circuit with the determined number of parallel pipeline stages is generated.
摘要翻译：提供了生成数据馈送特定解析器电路。接收与数据馈送特定分析器电路要处理的特定数据馈送相关联的馈送数据的字节数的输入。描述描述特定数据馈送的数据格式的馈送格式规范文件被解析以生成馈送格式规范文件的内部数据结构。基于生成的馈送格式指定文件的内部数据结构，确定数据馈送特定解析器电路中用于处理与特定数据相关联的馈送数据的字节数的最小数量的并行流水线级。然后，生成具有确定数量的并行流水线级的数据馈送特定分析器电路的描述。

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