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1. 发明授权

US06888213B2 Dielectric insulation structure for integrating electronic semiconductor devices and relevant manufacturing process 有权
标题翻译：用于集成电子半导体器件的绝缘绝缘结构及相关制造工艺
公开(公告)号：US06888213B2
公开(公告)日：2005-05-03
申请号：US10444102
申请日：2003-05-22
申请人： Salvatore Leonardi , Roberto Modica , Giuseppe Arena
发明人： Salvatore Leonardi , Roberto Modica , Giuseppe Arena
IPC分类号： H01L21/762 , H01L29/06
CPC分类号： H01L21/76264 , H01L21/76283
摘要： A dielectric insulation structure is formed in a silicon layer by integrating a dielectric trench structure therein. The dielectric trench structure defines an insulation well where semiconductor devices are to be integrated therein. The dielectric trench structure is on a hollow region that is completely surrounded by a dielectric area. The dielectric area also forms the side insulation of the dielectric trench structure. The dielectric trench structure is interrupted by a plurality of points to define a plurality of side support regions for the insulation well.
摘要翻译：通过在其中集成介电沟槽结构，在硅层中形成介电绝缘结构。电介质沟槽结构限定了将半导体器件集成在其中的绝缘阱。电介质沟槽结构在完全被电介质区域包围的中空区域上。电介质区域也形成电介质沟槽结构的侧绝缘体。电介质沟槽结构被多个点中断，以限定用于绝缘阱的多个侧支撑区域。

2. 发明申请

US20060194408A1 Process and circuit for manufacturing electronic semiconductor devices in a SOI substrate 有权
标题翻译：用于在SOI衬底中制造电子半导体器件的工艺和电路
公开(公告)号：US20060194408A1
公开(公告)日：2006-08-31
申请号：US11339815
申请日：2006-01-24
申请人： Salvatore Leonardi , Roberto Modica
发明人： Salvatore Leonardi , Roberto Modica
IPC分类号： H01L21/76
CPC分类号： H01L23/544 , H01L21/32 , H01L21/76286 , H01L21/8222 , H01L21/823481 , H01L21/823878 , H01L21/8249 , H01L29/66265 , H01L29/7317 , H01L29/7824 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A process for manufacturing an electronic semiconductor device, wherein a SOI wafer is provided, formed by a bottom layer of semiconductor material, an insulating layer, and a top layer of semiconductor material, stacked on top of one another; alignment marks are formed in the top layer; an implanted buried region is formed, aligned to the alignment marks; a hard mask is formed on top of the top layer so as to align it to the alignment marks; using the hard mask, the top layer is selectively removed so as to form a trench extending up to the insulating layer; there a lateral-insulation region in the trench, that is contiguous to the insulating layer and delimits with the latter an insulated well of semiconductor material; and electronic components are formed in the top layer.
摘要翻译：一种制造电子半导体器件的方法，其中SOI晶片由半导体材料的底层，绝缘层和半导体材料顶层形成，堆叠在彼此之上; 对准标记形成在顶层中; 形成与对准标记对准的注入掩埋区域; 在顶层的顶部形成硬掩模，以将其对准对准标记; 使用硬掩模，选择性地去除顶层，以形成延伸到绝缘层的沟槽; 在沟槽中存在横向绝缘区域，其与绝缘层相邻并且与绝缘层隔开半导体材料的绝缘阱; 并且电子部件形成在顶层中。

3. 发明授权

US07960244B2 Process for the aligned manufacture of electronic semiconductor devices in a SOI substrate 有权
标题翻译：用于在SOI衬底中对准制造电子半导体器件的工艺
公开(公告)号：US07960244B2
公开(公告)日：2011-06-14
申请号：US11339815
申请日：2006-01-24
申请人： Salvatore Leonardi , Roberto Modica
发明人： Salvatore Leonardi , Roberto Modica
IPC分类号： H01L21/76
CPC分类号： H01L23/544 , H01L21/32 , H01L21/76286 , H01L21/8222 , H01L21/823481 , H01L21/823878 , H01L21/8249 , H01L29/66265 , H01L29/7317 , H01L29/7824 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A process for manufacturing an electronic semiconductor device, wherein a SOI wafer is provided, formed by a bottom layer of semiconductor material, an insulating layer, and a top layer of semiconductor material, stacked on top of one another; alignment marks are formed in the top layer; an implanted buried region is formed, aligned to the alignment marks; a hard mask is formed on top of the top layer so as to align it to the alignment marks; using the hard mask, the top layer is selectively removed so as to form a trench extending up to the insulating layer; there a lateral-insulation region in the trench, that is contiguous to the insulating layer and delimits with the latter an insulated well of semiconductor material; and electronic components are formed in the top layer.
摘要翻译：一种制造电子半导体器件的方法，其中SOI晶片由半导体材料的底层，绝缘层和半导体材料顶层形成，堆叠在彼此之上; 对准标记形成在顶层中; 形成与对准标记对准的注入掩埋区域; 在顶层的顶部形成硬掩模，以将其对准对准标记; 使用硬掩模，选择性地去除顶层，以形成延伸到绝缘层的沟槽; 在沟槽中存在横向绝缘区域，其与绝缘层相邻并且与绝缘层隔开半导体材料的绝缘阱; 并且电子部件形成在顶层中。

4. 发明申请

US20060125049A1 Resistive structure integrated in a semiconductor substrate 审中-公开
标题翻译：集成在半导体衬底中的电阻结构
公开(公告)号：US20060125049A1
公开(公告)日：2006-06-15
申请号：US11333114
申请日：2006-01-17
申请人： Salvatore Leonardi , Roberto Modica
发明人： Salvatore Leonardi , Roberto Modica
IPC分类号： H01L29/00
CPC分类号： H01L28/20 , H01L27/0802
摘要： A resistive structure integrated in a semiconductor substrate and having a suitably doped polysilicon region that is completely surrounded by a dielectric region so that the resistive structure is isolated electrically from other components jointly integrated in the semiconductor substrate.
摘要翻译：一种电阻结构，其集成在半导体衬底中并且具有完全被介电区域包围的适当掺杂的多晶硅区域，使得该电阻结构与联合地集成在该半导体衬底中的其它部件电隔离。

5. 发明授权

US06614094B2 High integration density vertical capacitor structure and fabrication process 有权
标题翻译：高集成度垂直电容器结构和制造工艺
公开(公告)号：US06614094B2
公开(公告)日：2003-09-02
申请号：US09747167
申请日：2000-12-21
申请人： Salvatore Leonardi , Roberto Modica
发明人： Salvatore Leonardi , Roberto Modica
IPC分类号： H01L2900
CPC分类号： H01L27/10861 , H01L28/40 , H01L29/66181
摘要： A vertical capacitor structure fabricated in a semiconductor substrate region overlaid by a buried oxide layer and a buried doped layer, as well as by a semiconductor layer that includes a sinker doped region in contact with the buried doped layer, wherein an oxide trench structure is formed, this oxide trench structure being filled with suitably doped polysilicon to produce, in combination with the sinker region, the plates of the vertical capacitor structure, with the oxide trench structure forming the dielectric therebetween. A process for integrating a vertical capacitor structure starting from a structure blank that includes a semiconductor substrate, a buried oxide layer and a buried doped layer is also provided.
摘要翻译：在由掩埋氧化物层和掩埋掺杂层覆盖的半导体衬底区域中制造的垂直电容器结构以及包括与掩埋掺杂层接触的沉降片掺杂区的半导体层，其中形成氧化物沟槽结构，该氧化物沟槽结构填充有适当掺杂的多晶硅，以与沉降片区域组合产生垂直电容器结构的板，其中氧化物沟槽结构在其间形成电介质。还提供了一种从包括半导体衬底，掩埋氧化物层和掩埋掺杂层的结构坯料开始积分垂直电容器结构的工艺。

6. 发明授权

US08575720B2 Process for integrating on an inert substrate a device comprising at least a passive element and an active element and corresponding integrated device 有权
标题翻译：用于在惰性基板上集成至少包括无源元件和有源元件的器件以及相应的集成器件的工艺
公开(公告)号：US08575720B2
公开(公告)日：2013-11-05
申请号：US11803716
申请日：2007-05-14
申请人： Salvatore Leonardi , Salvatore Coffa , Claudia Caligiore , Francesca Paola Tramontana
发明人： Salvatore Leonardi , Salvatore Coffa , Claudia Caligiore , Francesca Paola Tramontana
IPC分类号： H01L27/08
CPC分类号： H01L21/84 , H01L27/12
摘要： A process is described for integrating, on an inert substrate, a device having at least one passive component and one active component. The process comprises: deposition of a protection dielectric layer on the inert substrate; formation of a polysilicon island on the protection dielectric layer; integration of the active component on the polysilicon island; deposition of the covering dielectric layer on the protection dielectric layer and on the active component; integration of the passive component on the covering dielectric layer; formation of first contact structures in openings realised in the covering dielectric layer in correspondence with active regions of the active component; and formation of second contact structures in correspondence with the passive component. An integrated device obtained through this process is also described.
摘要翻译：描述了一种在惰性基板上集成具有至少一个无源部件和一个有源部件的装置的方法。该方法包括：将保护电介质层沉积在惰性衬底上; 在保护电介质层上形成多晶硅岛; 有源元件在多晶硅岛上的集成; 覆盖电介质层沉积在保护电介质层和有源元件上; 将被动元件集成在覆盖介电层上; 在与所述有源部件的有源区域对应的覆盖介电层中实现的开口中形成第一接触结构; 以及与被动部件对应地形成第二接触结构。还描述了通过该方法获得的集成装置。

7. 发明授权

US07952104B2 Thin-film transistor (TFT) device 有权
标题翻译：薄膜晶体管（TFT）器件
公开(公告)号：US07952104B2
公开(公告)日：2011-05-31
申请号：US12564719
申请日：2009-09-22
申请人： Salvatore Leonardi , Claudia Caligiore
发明人： Salvatore Leonardi , Claudia Caligiore
IPC分类号： H01L29/04 , H01L31/036
CPC分类号： H01L21/02686 , H01L21/02488 , H01L21/02532 , H01L21/2026 , H01L27/1229 , H01L27/1281 , H01L29/66757
摘要： A process for manufacturing a thin-film transistor device includes forming a dielectric insulation layer on a substrate, forming an amorphous silicon layer on the dielectric insulation layer, crystallizing the amorphous silicon layer, so as to obtain polycrystalline silicon, forming gate structures on the polycrystalline silicon, and forming first doped regions within the polycrystalline silicon laterally with respect to the gate structures. The crystallizing step includes forming first capping dielectric regions on the amorphous silicon layer, and then irradiating the amorphous silicon layer using a laser so as to form active areas of polycrystalline silicon separated by separation portions of amorphous silicon underlying the first capping dielectric regions.
摘要翻译：一种薄膜晶体管器件的制造方法，其特征在于，在基板上形成介电绝缘层，在所述绝缘层上形成非晶硅层，使所述非晶硅层结晶化，得到多晶硅，在所述多晶硅上形成栅极结构硅，并且相对于栅极结构横向地在多晶硅内形成第一掺杂区域。所述结晶步骤包括在所述非晶硅层上形成第一覆盖电介质区域，然后使用激光照射所述非晶硅层，以便形成由所述第一覆盖电介质区域下方的非晶硅的分离部分分离的多晶硅的有源区域。

8. 发明申请

US20100163759A1 RADIATION SENSOR WITH PHOTODIODES BEING INTEGRATED ON A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING INTEGRATION PROCESS 审中-公开
标题翻译：带有光电转换器的辐射传感器集成在半导体衬底和相应的集成工艺
公开(公告)号：US20100163759A1
公开(公告)日：2010-07-01
申请号：US12649256
申请日：2009-12-29
申请人： Maria Eloisa Castagna , Salvatore Leonardi , Salvatore Abbisso , Lidia Maddiona
发明人： Maria Eloisa Castagna , Salvatore Leonardi , Salvatore Abbisso , Lidia Maddiona
IPC分类号： H01L31/14 , H01L31/0216 , H01L31/18
CPC分类号： H01L31/18 , G01J1/0488 , G01J1/4204 , G01J1/4228 , H01L27/1443 , H01L31/02165
摘要： An embodiment relates to a sensor integrated on a semiconductor substrate and comprising at least one first and second photodiode including at least one first and one second p-n junction made in such a semiconductor substrate as well as at least one first and one second antireflection coating made on top of such a first and second photodiode. At least one antireflection coating of such a first and second photodiode comprises at least one first and one second different antireflection layer to make a double layer antireflection coating suitable for obtaining for the corresponding photodiode a responsivity peak at a predetermined wavelength of an optical signal incident on the sensor. An embodiment also refers to an integration process of such a sensor, as well as to an ambient light sensor made with such a sensor.
摘要翻译：实施例涉及集成在半导体衬底上并包括至少一个第一和第二光电二极管的传感器，该至少一个第一和第二光电二极管包括在这种半导体衬底中形成的至少一个第一和一个第二pn结，以及至少一个第一和第二反射防止涂层这样的第一和第二光电二极管的顶部。这种第一和第二光电二极管的至少一个抗反射涂层包括至少一个第一和第二不同的抗反射层，以制造双层抗反射涂层，其适合于为相应的光电二极管获得在入射到其上的光信号的预定波长的响应峰传感器。实施例还涉及这种传感器以及由这种传感器制成的环境光传感器的集成过程。

9. 发明申请

US20070148527A1 FUEL CELL PLANARLY INTEGRATED ON A MONOCRYSTALLINE SILICON CHIP AND PROCESS OF FABRICATION 有权
标题翻译：燃料电池平面集成在单晶硅芯片和制造工艺
公开(公告)号：US20070148527A1
公开(公告)日：2007-06-28
申请号：US11611521
申请日：2006-12-15
申请人： Simone Siciliano , Luigi La Magna , Salvatore Leonardi
发明人： Simone Siciliano , Luigi La Magna , Salvatore Leonardi
IPC分类号： H01M8/02 , H01M4/86 , H01M4/88 , B05D5/12 , C25D5/02 , C25D3/00
CPC分类号： H01M8/1097 , H01M8/0271 , H01M8/04089 , H01M8/241 , H01M8/2425 , H01M2008/1095
摘要： A fuel cell is entirely fabricated on a single monocrystalline silicon substrate, and substantially overcomes leak proofing and wafer bonding difficulties and criticalities while ensuring an intrinsic sturdiness of the planarly integrated functional structure of the fuel cell. The integrated fuel cell is formed in an oxidized porous silicon region on a monocrystalline silicon substrate that is pervious to fluid flow and is electrically nonconductive with the monocrystalline silicon substrate.
摘要翻译：燃料电池完全制造在单个单晶硅衬底上，并且基本上克服了防漏和晶片接合困难和临界，同时确保燃料电池的平面集成的功能结构的内在坚固性。集成的燃料电池形成在单晶硅衬底上的氧化的多孔硅区域中，该单晶硅衬底可渗透流体流动并且与单晶硅衬底不导电。

10. 发明申请

US20070034872A1 Process for manufacturing a thin-film transistor (TFT) device and TFT device manufactured by the process 有权
标题翻译：用于制造薄膜晶体管（TFT）器件和通过该工艺制造的TFT器件的工艺
公开(公告)号：US20070034872A1
公开(公告)日：2007-02-15
申请号：US11478332
申请日：2006-06-28
申请人： Salvatore Leonardi , Claudia Caligiore
发明人： Salvatore Leonardi , Claudia Caligiore
IPC分类号： H01L29/04
CPC分类号： H01L21/02686 , H01L21/02488 , H01L21/02532 , H01L21/2026 , H01L27/1229 , H01L27/1281 , H01L29/66757
摘要： A process for manufacturing a thin-film transistor device includes forming a dielectric insulation layer on a substrate, forming an amorphous silicon layer on the dielectric insulation layer, crystallizing the amorphous silicon layer, so as to obtain polycrystalline silicon, forming gate structures on the polycrystalline silicon, and forming first doped regions within the polycrystalline silicon laterally with respect to the gate structures. The crystallizing step includes forming first capping dielectric regions on the amorphous silicon layer, and then irradiating the amorphous silicon layer using a laser so as to form active areas of polycrystalline silicon separated by separation portions of amorphous silicon underlying the first capping dielectric regions.
摘要翻译：一种薄膜晶体管器件的制造方法，其特征在于，在基板上形成介电绝缘层，在所述绝缘层上形成非晶硅层，使所述非晶硅层结晶化，得到多晶硅，在所述多晶硅上形成栅极结构硅，并且相对于栅极结构横向地在多晶硅内形成第一掺杂区域。所述结晶步骤包括在所述非晶硅层上形成第一覆盖电介质区域，然后使用激光照射所述非晶硅层，以便形成由所述第一覆盖电介质区域下方的非晶硅的分离部分分离的多晶硅的有源区域。

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