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    • 4. 发明授权
    • Thin-film transistor (TFT) device
    • 薄膜晶体管(TFT)器件
    • US07952104B2
    • 2011-05-31
    • US12564719
    • 2009-09-22
    • Salvatore LeonardiClaudia Caligiore
    • Salvatore LeonardiClaudia Caligiore
    • H01L29/04H01L31/036
    • H01L21/02686H01L21/02488H01L21/02532H01L21/2026H01L27/1229H01L27/1281H01L29/66757
    • A process for manufacturing a thin-film transistor device includes forming a dielectric insulation layer on a substrate, forming an amorphous silicon layer on the dielectric insulation layer, crystallizing the amorphous silicon layer, so as to obtain polycrystalline silicon, forming gate structures on the polycrystalline silicon, and forming first doped regions within the polycrystalline silicon laterally with respect to the gate structures. The crystallizing step includes forming first capping dielectric regions on the amorphous silicon layer, and then irradiating the amorphous silicon layer using a laser so as to form active areas of polycrystalline silicon separated by separation portions of amorphous silicon underlying the first capping dielectric regions.
    • 一种薄膜晶体管器件的制造方法,其特征在于,在基板上形成介电绝缘层,在所述绝缘层上形成非晶硅层,使所述非晶硅层结晶化,得到多晶硅,在所述多晶硅上形成栅极结构 硅,并且相对于栅极结构横向地在多晶硅内形成第一掺杂区域。 所述结晶步骤包括在所述非晶硅层上形成第一覆盖电介质区域,然后使用激光照射所述非晶硅层,以便形成由所述第一覆盖电介质区域下方的非晶硅的分离部分分离的多晶硅的有源区域。
    • 8. 发明授权
    • High-voltage semiconductor device with integrated edge structure and
associated manufacturing process
    • 具有集成边缘结构和相关制造工艺的高压半导体器件
    • US5796156A
    • 1998-08-18
    • US671851
    • 1996-06-28
    • Salvatore LeonardiDavide Bolognesi
    • Salvatore LeonardiDavide Bolognesi
    • H01L29/06H01L23/58
    • H01L29/0619H01L29/0615
    • A semiconductor device including a substrate having a first conductivity type on which are formed first and second epitaxial layers of the same conductivity type of the substrate. The semiconductor device also includes a first diffused region having a second conductivity type formed in a first portion of the first and second epitaxial layers. Said first diffused region defines a first junction with said first and second epitaxial layers. The semiconductor device also comprises an edge structure having the second conductivity type formed in a second portion of the first and second epitaxial layers. The edge structure includes a second diffused region having the second conductivity type formed in the first and second epitaxial layers, said second diffused region defining a second junction with said first and second epitaxial layers. The edge structure also includes a third diffused region of the same conductivity type of the second diffused region formed in the second epitaxial layer, said third diffused region being interposed between the first and the second diffuse regions and defining a third junction with said second epitaxial layer, said third junction being shallower than the first and the second junctions.
    • 一种半导体器件,包括具有第一导电类型的衬底,其上形成有相同导电类型的衬底的第一和第二外延层。 半导体器件还包括形成在第一和第二外延层的第一部分中的具有第二导电类型的第一扩散区域。 所述第一扩散区域限定与所述第一和第二外延层的第一结。 半导体器件还包括在第一和第二外延层的第二部分中形成的具有第二导电类型的边缘结构。 边缘结构包括形成在第一和第二外延层中的具有第二导电类型的第二扩散区域,所述第二扩散区域限定与所述第一和第二外延层的第二结。 边缘结构还包括形成在第二外延层中的与第二扩散区相同导电类型的第三扩散区,所述第三扩散区介于第一和第二扩散区之间,并且与所述第二外延层 所述第三结点比所述第一和第二结点浅。