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1. 发明授权

US5012122A Circuit to inhibit voltage and current returns to the electric power distribution line in an inverter-type power plant 失效
标题翻译：逆变器型发电厂的电力分配线回路抑制电压和电流回路
公开(公告)号：US5012122A
公开(公告)日：1991-04-30
申请号：US424241
申请日：1989-10-20
申请人： Salvatore Lentini , Giuseppe Patti
发明人： Salvatore Lentini , Giuseppe Patti
IPC分类号： H02J7/06 , H02J9/06
CPC分类号： H02J9/062 , Y10T307/516 , Y10T307/729
摘要： The present invention is applicable for inverter-type power plants where the electric distribution line is used as stand-by unit. The present invention is composed of a ballast impedance and an electric mesh including an energizing circuit of a first section suitable for insulating a power plant from the distribution line; contacts of a second section which are monitored by a supervisory control circuit of the power plant; and an electric probe for making available a voltage or a current measurement when current flows through the distribution line.
摘要翻译： PCT No.PCT / EP88 / 00327 Sec。 371日期1989年10月20日第 102（e）日期1989年10月20日PCT提交1988年4月4日PCT公布。出版物WO88 / 09075 日期：1988年11月17日。本发明适用于配电线路作为备用机组的逆变式发电厂。本发明由镇流器阻抗和电网组成，包括适于将发电厂从分配线绝缘的第一部分的通电电路; 由发电厂的监控控制电路监测的第二部分的触点; 以及电流探针，用于当电流流过配电线路时提供电压或电流测量。

2. 发明授权

US4886981A Synchronizing circuit for a plurality of power units 失效
标题翻译：用于多个功率单元的同步电路
公开(公告)号：US4886981A
公开(公告)日：1989-12-12
申请号：US10137
申请日：1987-02-03
申请人： Salvatore Lentini , Giuseppe Patti
发明人： Salvatore Lentini , Giuseppe Patti
IPC分类号： H02J1/10 , H02J3/38 , H04J3/06
CPC分类号： H04J3/0688 , H02J1/102 , H02J3/38 , H02J2001/104 , Y10T307/735
摘要： A power system includes as many synchronizing units as the number of the power units. Each synchronizing unit has been designed to receive an activation signal at its input and to be connected to the other units through of a first and a second discs. Each synchronizing unit delivers to its output a synchronizing clock signal for the respective power units. The first synchronizing unit which receives the activation signal is qualified as the master unit. This master unit applies a predetermined polarity to the first bus and a clock signal to the second bus in order to synchronize the other units in response to the detection of the polarity on the first bus, the other units are characterized as slave unit.
摘要翻译： PCT No.PCT / EP76 / 00369 Sec。 371日期1987年2月3日 102（e）日期1987年2月3日PCT Filed 1986年6月20日PCT公布。公开号WO87 / 00701 日期1987年1月29日。电力系统包括与电力单元数量一样多的同步单元。每个同步单元被设计成在其输入处接收激活信号，并且通过第一和第二光盘连接到其它单元。每个同步单元向其输出端递送各个功率单元的同步时钟信号。接收激活信号的第一同步单元被认定为主单元。该主单元将第一总线的预定极性和第二总线的时钟信号施加到第二总线上，以便响应于第一总线上的极性检测而使其他单元同步，其他单元被表征为从单元。

3. 发明授权

US4841161A Monitoring circuit for control means and selective breakaway means in modular supply systems 失效
标题翻译：控制装置的监控电路和模块化供电系统中的选择性分离装置
公开(公告)号：US4841161A
公开(公告)日：1989-06-20
申请号：US10281
申请日：1987-02-02
申请人： Salvatore Lentini , Giuseppe Patti
发明人： Salvatore Lentini , Giuseppe Patti
IPC分类号： G05F1/59 , H02J1/10
CPC分类号： G05F1/59 , H02J1/102 , Y10T307/50 , Y10T307/724
摘要： Modular supply systems usually include a plurality of n elementary power units, connected in parallel to each other. Control unit (RV) and selective breakaway unit (DS) are associated with each elementary power unit. The monitoring circuit (CP) includes a first device (PM) which calculates the entity of the deviation (E) between a signal (Iu.sub.i) that is proportional to the current supplied by the relevant power unit (UA.sub.i) and a signal (I.sub.med) that is proportional to the average value of the currents supplied by the n power units. Also, a second device (SM) algebraically sums the deviation (E) to a signal (Vu.sub.i) that is proportional to the voltage available on the output of the relevant power unit. The signal (Vc) that is available on the output of the second device is delivered to the control unit (RV) and the selective breakaway unit (DS).
摘要翻译： PCT No.PCT / EP86 / 00415 Sec。 371日期1987年2月2日 102（e）1987年2月2日PCT PCT。1986年7月15日PCT公布。公开号WO87 / 00655 日期1987年1月29日。模块化供应系统通常包括彼此并联连接的多个n个基本功率单元。控制单元（RV）和选择性分离单元（DS）与每个基本功率单元相关联。监控电路（CP）包括第一设备（PM），其计算与由相关电力单元（UAi）提供的电流成比例的信号（Iui）与信号（Imed）之间的偏差（E）的实体，这与n个功率单元提供的电流的平均值成比例。而且，第二装置（SM）代数地将偏差（E）与与相关功率单元的输出上可用的电压成比例的信号（Vui）相加。在第二设备的输出上可用的信号（Vc）被传送到控制单元（RV）和选择性分离单元（DS）。

4. 发明授权

US06556366B2 Bimodal biasing of magneto resistive heads 有权
标题翻译：磁阻头的双模偏置
公开(公告)号：US06556366B2
公开(公告)日：2003-04-29
申请号：US09944265
申请日：2001-08-30
申请人： Giuseppe Patti , Axel Alegre de La Soujeole
发明人： Giuseppe Patti , Axel Alegre de La Soujeole
IPC分类号： G11B503
CPC分类号： G11B5/012 , G11B5/02 , G11B5/09 , G11B5/40 , G11B5/455 , G11B19/02 , G11B2005/0018
摘要： A system and method for selecting between two biasing modes for biasing magneto resistive heads in a disk drive. A mode selector selects either a voltage biasing circuit or a current biasing to supply the bias voltage or bias current, respectively, to a magneto resistive head. The selection can be based on changes in parameters in the disk drive or magneto resistive heads during disk drive operation.
摘要翻译：用于在用于偏置磁盘驱动器中的磁阻头的两种偏压模式之间进行选择的系统和方法。模式选择器分别选择电压偏置电路或电流偏置以将偏置电压或偏置电流分别提供给磁阻头。该选择可以基于在磁盘驱动器操作期间磁盘驱动器或磁阻磁头中的参数的变化。

5. 发明授权

US5805015A Current generator stage used with integrated analog circuits 失效
标题翻译：电流发生器级与集成模拟电路一起使用
公开(公告)号：US5805015A
公开(公告)日：1998-09-08
申请号：US629320
申请日：1996-04-08
申请人： Melchiorre Bruccoleri , Gaetano Cosentino , Marco Demicheli , Giuseppe Patti
发明人： Melchiorre Bruccoleri , Gaetano Cosentino , Marco Demicheli , Giuseppe Patti
IPC分类号： G05F3/22 , G05F3/26 , H03F3/343 , H03K17/04 , H03K17/60 , G05F3/16
CPC分类号： G05F3/265 , G05F3/222
摘要： A current generator stage for integrated analog circuits includes a current source connected between a supply voltage and a ground terminal. A current mirror is operationally connected to the current source to generate an output current. A bias circuit is operationally connected to the current source to perform switching of the current source from a first operating mode to a second operating mode. The bias circuit includes an energy storage circuit which, in a first circuit configuration, supplies to the current source a first predetermined voltage when the current source is in the first operating mode. The energy storage circuit in a second circuit configuration is a combination of first and second reactances to supply to the current source a second predetermined voltage when the current source is in the second operating mode.
摘要翻译：用于集成模拟电路的电流发生器级包括连接在电源电压和接地端子之间的电流源。电流镜可操作地连接到电流源以产生输出电流。偏置电路可操作地连接到电流源，以将电流源从第一操作模式切换到第二操作模式。偏置电路包括能量存储电路，其在第一电路配置中，当电流源处于第一操作模式时，向电流源提供第一预定电压。第二电路配置中的能量存储电路是第一和第二电抗的组合，以在电流源处于第二操作模式时向电流源提供第二预定电压。

6. 发明授权

US06512645B1 Circuit and method for writing to a memory disk with a boosted voltage 有权
标题翻译：用升压电压写入存储盘的电路和方法
公开(公告)号：US06512645B1
公开(公告)日：2003-01-28
申请号：US09393231
申请日：1999-09-09
申请人： Giuseppe Patti , Roberto Alini , Elango Pakriswamy
发明人： Giuseppe Patti , Roberto Alini , Elango Pakriswamy
IPC分类号： G11B509
CPC分类号： G11B5/022 , G11B5/012 , G11B5/02 , G11B5/09
摘要： A method and circuit are disclosed for controlling the write head of a magnetic disk storage device. The circuit includes a pull-up device coupled to a terminal of the write head, a current sink circuit which is coupled to the write head terminal and a bootstrap circuit coupled to the current sink circuit. When reversing the direction of current flow through the write head so that current is drawn from the write head from the write head terminal, the bootstrap circuit and the current sink circuit are activated. When the current in the write head nears and/or slightly surpasses the desired destination current level, the bootstrap circuit is deactivated and the pull-up device is thereafter immediately activated for a predetermined period of time.
摘要翻译：公开了一种用于控制磁盘存储装置的写入头的方法和电路。电路包括耦合到写头的端子的上拉装置，耦合到写入头端子的电流吸收电路和耦合到电流吸收电路的自举电路。当逆向通过写入头的电流的方向使得电流从写入头从写入头抽出时，自举电路和电流吸收电路被激活。当写头中的电流接近和/或稍微超过期望的目的地电流电平时，自举电路被去激活，然后上拉装置立即激活预定时间段。

7. 发明授权

US6043943A Asymmetry correction for a read head 失效
标题翻译：读头的不对称校正
公开(公告)号：US6043943A
公开(公告)日：2000-03-28
申请号：US846782
申请日：1997-04-30
申请人： Francesco Rezzi , Giuseppe Patti
发明人： Francesco Rezzi , Giuseppe Patti
IPC分类号： G11B5/09 , G11B5/00 , G11B5/012 , G11B5/02 , G11B5/39 , G11B20/10
CPC分类号： G11B5/012 , G11B20/10009 , G11B5/09 , G11B2005/0016
摘要： A method and a circuit for correcting asymmetry in a response signal generated by a magneto-resistive head. The magneto-resistive head generates a response signal to transmit digital information read from a magnetic media storage device. The asymmetry is corrected in a negative feedback manner by squaring an output signal, modulating the squared output signal, and subtracting the modulated squared output signal from the response signal to generate the output signal. The circuit employs a differential amplifier as an input stage and a Gilbert multiplier circuit to square the output signal.
摘要翻译：一种用于校正由磁阻头产生的响应信号中的不对称的方法和电路。磁阻头产生响应信号以传送从磁性介质存储装置读取的数字信息。通过平方输出信号，调制平方输出信号，以及从响应信号中减去经调制的平方输出信号以产生输出信号，以负反馈方式校正不对称性。该电路采用差分放大器作为输入级和吉尔伯特乘法器电路对输出信号进行平方。

8. 发明授权

US5748128A Reduced current quadratic digital/analog converter with improved settling-time 失效
标题翻译：减少电流二次数字/模拟转换器，提高了建立时间
公开(公告)号：US5748128A
公开(公告)日：1998-05-05
申请号：US645457
申请日：1996-05-13
申请人： Melchiorre Bruccoleri , Marco Demicheli , Giuseppe Patti , Valerio Pisati
发明人： Melchiorre Bruccoleri , Marco Demicheli , Giuseppe Patti , Valerio Pisati
IPC分类号： H03M1/68 , G06J1/00 , H03M1/66 , H03M1/78 , H03M1/16
CPC分类号： H03M1/664 , G06J1/00 , H03M1/785
摘要： A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.
摘要翻译：由串联连接的一对线性转换器组成的数字/模拟二次转换器（DACQ）具有第一转换器（DAC1）的输出节点与第二转换器的R-2R型电阻网络的节点的直接耦合 DAC2）对应于R-2R型电阻网络的LSB级。有利地，从“电流路径”消除高阻抗节点，特别是第二线性转换器的输入节点，从而显着地减少了高阻抗节点（具有与其相关的本质上大的寄生电容）的较长建立时间的问题。二次转换器的独特结构也为电路的显着简化提供了依据。

9. 发明授权

US06456148B2 Circuit and method for writing to a memory disk 有权
标题翻译：用于写入存储盘的电路和方法
公开(公告)号：US06456148B2
公开(公告)日：2002-09-24
申请号：US09839511
申请日：2001-04-20
申请人： Giuseppe Patti , Roberto Alini , Gilles P. DeNoyer
发明人： Giuseppe Patti , Roberto Alini , Gilles P. DeNoyer
IPC分类号： H03K1756
CPC分类号： G11B5/022 , G11B5/012 , G11B5/02 , G11B5/09
摘要： A method and circuit are disclosed for controlling the write head of a magnetic disk storage device. The circuit includes a pull-up device coupled to a terminal of the write head, for selectively providing a current to the write head though the write head terminal. The circuit further includes parallel-connected current sink circuits, each of which is coupled to the write head terminal and selectively activated to draw current from the write head via the write head terminal. A first transistor is connected in series between the pull-up device and the write head terminal and biased to provide a voltage differential between the write head terminal and the pull-up device. A second transistor is connected in series between the write head terminal and the current sink circuits and biased to provide a voltage differential between the write head terminal and the current sink circuits.
摘要翻译：公开了一种用于控制磁盘存储装置的写入头的方法和电路。该电路包括耦合到写入头的终端的上拉装置，用于通过写入头终端选择性地向写入头提供电流。电路还包括并联连接的电流吸收电路，每个电路都耦合到写入头终端，并被选择性地激活以经由写头终端从写入头抽取电流。第一晶体管串联连接在上拉器件和写入端子之间，并被偏置以在写入头端子和上拉器件之间提供电压差。第二晶体管串联连接在写入头端子和电流吸收电路之间，并被偏置以在写入头端子和电流吸收电路之间提供电压差。

10. 发明授权

US06359743B1 Apparatus and method for reducing thermal interference in MR heads in disk drives 有权
标题翻译：用于减少磁盘驱动器中MR磁头的热干扰的装置和方法
公开(公告)号：US06359743B1
公开(公告)日：2002-03-19
申请号：US09197122
申请日：1998-11-20
申请人： Giuseppe Patti , Eugene C. Lee , Roberto Alini
发明人： Giuseppe Patti , Eugene C. Lee , Roberto Alini
IPC分类号： G11B502
CPC分类号： G11B5/012 , G11B2005/0016
摘要： An apparatus (and method) is provided that reduces thermal interference in the read signal of a disk drive. A variable or programmable resistance is used to change the transfer function of a filter in the read channel of the disk drive to filter the read signal. The filter has a first transfer function (first cut-off frequency) related to the programmed resistance during normal operation of the disk drive (i.e. when thermal interference is not detected). When thermal interference is detected in the read signal, the resistance is programmed to another value resulting in the filter having a second transfer function (second cut-off frequency). The resistance element is variable or programmable to different values resulting in different programmable transfer functions (or one of a multitude of cut-off frequencies) for the filter. In the preferred embodiment, detection of thermal interference increases the cut-off frequency of the filter thereby filtering, or reducing the effects of, the thermal interference in the read signal.
摘要翻译：提供了减少磁盘驱动器的读取信号中的热干扰的装置（和方法）。使用可变或可编程电阻来改变磁盘驱动器的读通道中的滤波器的传递函数，以过滤读取信号。滤波器在磁盘驱动器的正常操作期间（即，当未检测到热干扰时）具有与编程电阻相关的第一传递函数（第一截止频率）。当在读取信号中检测到热干扰时，电阻被编程为另一个值，导致滤波器具有第二传递函数（第二截止频率）。电阻元件可变或可编程为不同的值，导致滤波器的不同可编程传输功能（或多个截止频率之一）。在优选实施例中，热干扰的检测增加了滤波器的截止频率，从而过滤或减少了读取信号中的热干扰的影响。

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