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1. 发明授权

US6060913A Electrical system with small signal suppression circuitry 失效
标题翻译：具有小信号抑制电路的电气系统
公开(公告)号：US6060913A
公开(公告)日：2000-05-09
申请号：US918307
申请日：1997-08-26
申请人： Salomon Vulih , Stephen J. Glica , Harold Allen Wittlinger
发明人： Salomon Vulih , Stephen J. Glica , Harold Allen Wittlinger
IPC分类号： F02P5/15
CPC分类号： F02D35/027 , F02D41/28 , F02D2041/1432
摘要： In systems embodying the invention, circuitry responsive to first and second, complementary, input signals controls the application of the input signals to a positive signal integrator and to a negative signal integrator. When the amplitude of the input signals is greater than a predetermined value, the one of the two input signals which is positive relative to the other is applied to the positive signal integrator and the other one of the two input signals is applied to the negative signal integrator. When the amplitude of the input signals is smaller than a predetermined level, the circuitry causes the periodic application of the first input signal to the positive signal integrator and the second input signal to the negative signal integrator during one time interval, and the periodic application of the first input signal to the negative signal integrator and the second input signal to the positive signal integrator during a second, subsequent, time interval of similar duration as the one time interval.
摘要翻译：在体现本发明的系统中，响应于第一和第二互补输入信号的电路控制输入信号施加到正信号积分器和负信号积分器。当输入信号的幅度大于预定值时，相对于另一个输入信号为正的两个输入信号中的一个被施加到正信号积分器，并且两个输入信号中的另一个被施加到负信号集成商当输入信号的幅度小于预定电平时，电路使得在一个时间间隔内将第一输入信号周期性地应用于正信号积分器和第二输入信号到负信号积分器，并且周期性地施加在与一个时间间隔相似的持续时间的第二后续时间间隔期间，将负信号积分器的第一输入信号和到第二输入信号的正信号积分器。

2. 发明授权

US5942677A Knock sensor system for detecting and responding to a disconnect condition 失效
标题翻译：用于检测和响应断开状态的敲击传感器系统
公开(公告)号：US5942677A
公开(公告)日：1999-08-24
申请号：US931340
申请日：1997-09-16
申请人： Salomon Vulih , Stephen J. Glica , Harold Allen Wittlinger
发明人： Salomon Vulih , Stephen J. Glica , Harold Allen Wittlinger
IPC分类号： G01L23/22
CPC分类号： G01L23/225
摘要： Signals generated by a knock sensor are coupled to an electronic network for amplifying and processing the output signals of the knock sensor. The electronic network includes a device for charging a storage capacitor to a potential which is a function of the amplitude of the knock sensor output signal. The storage capacitor is coupled to the input of an amplifier via a normally closed first switch. A detector for sensing any disconnection of the knock sensor from the electronic system produces a control signal indicative of a disconnect condition. The control signal is used to open the normally closed first switch and to cause the input of the amplifier to be clamped to a reference potential which lies outside the signal range normally produced across the storage capacitor whereby the output of the output of the amplifier is placed at a predetermined level indicative of a disconnect condition. The amplifier thus produces signals at its output which are within a predetermined range during normal operation and a signal outside of this range in response to a knock sensor disconnect condition. Thus, a single line from the output amplifier carries regular normal signals and the disconnect signal lying outside the range of the normal signals.
摘要翻译：由爆震传感器产生的信号耦合到电子网络，用于放大和处理爆震传感器的输出信号。电子网络包括用于将存储电容器充电到与爆震传感器输出信号的幅度有关的电位的装置。存储电容器通过常闭的第一开关耦合到放大器的输入端。用于感测爆震传感器与电子系统的任何断开的检测器产生指示断开状态的控制信号。控制信号用于打开常闭的第一开关，并且使放大器的输入被钳位到参考电位，该参考电位位于通常在存储电容器两端产生的信号范围之外，从而放大放大器的输出端处于指示断开状态的预定水平。因此，放大器在其输出处产生在正常操作期间在预定范围内的信号，并且响应于爆震传感器断开状态而在该范围之外的信号。因此，来自输出放大器的单线承载常规的正常信号，断开信号位于正常信号的范围之外。

3. 发明授权

US5892375A Comparator with small signal suppression circuitry 失效
标题翻译：具有小信号抑制电路的比较器
公开(公告)号：US5892375A
公开(公告)日：1999-04-06
申请号：US918345
申请日：1997-08-26
申请人： Salomon Vulih , Stephen J. Glica , Harold Allen Wittlinger
发明人： Salomon Vulih , Stephen J. Glica , Harold Allen Wittlinger
IPC分类号： H03K5/1252 , H03K5/24 , H03K5/22
CPC分类号： H03K5/249 , H03K5/1252 , H03K5/2481
摘要： A comparator circuit has first and second inputs and an output and includes means for operating the comparator in alternate autozero and comparator phases. During an autozero phase, the inputs of the comparator are clamped to a reference potential and during a compare phase, input signals are applied to the input of the comparator. Control signals are applied to the inputs of the comparator during a portion of the compare phase. The control signals determine the state of the comparator output when the input signals applied to the inputs of the comparator are below a predetermined level.
摘要翻译：比较器电路具有第一和第二输入和输出，并且包括用于在替代自动调零和比较器相位中操作比较器的装置。在自动调零阶段，比较器的输入被钳位到参考电位，而在比较阶段，输入信号被加到比较器的输入端。在比较阶段的一部分期间，控制信号被施加到比较器的输入。当施加到比较器的输入的输入信号低于预定电平时，控制信号确定比较器输出的状态。

4. 发明授权

US5142244A Full range input/output comparator 失效
标题翻译：全范围输入/输出比较器
公开(公告)号：US5142244A
公开(公告)日：1992-08-25
申请号：US696481
申请日：1991-05-06
申请人： Stephen J. Glica , John A. Olmstead
发明人： Stephen J. Glica , John A. Olmstead
IPC分类号： H03F3/30 , H03F3/45 , H03K5/08
CPC分类号： H03F3/4521 , H03F3/303 , H03F2203/30057 , H03F2203/45508 , H03F2203/45674
摘要： A comparator circuit includes first and second differential amplifier input stages to which are applied the same differential input signals with each stage being powered by first (V1) and second (V2) operating potentials. The first stage is only responsive to differential input signals ranging in value between V1 and a first state threshold voltage (V.sub.T1) above V2. The second state is only responsive to differential input signals ranging in value between V2 and a second state threshold (V.sub.T2) below V1. Each one of the first and second stages, when operative, produces output signals which can swing fully between V1 and V2 as a function of the input signals. The output signals of the first and second stages are combined in an OR'ing circuit to produce an output signal whose amplitude can swing over the full operating voltage applied to the first and second supply lines for values of differential input signals ranging between V1 and V2.

5. 发明授权

US5262689A BIMOS current driver circuit 失效
标题翻译： BIMOS电流驱动电路
公开(公告)号：US5262689A
公开(公告)日：1993-11-16
申请号：US781626
申请日：1991-10-24
申请人： Stephen J. Glica , Raymond L. Giordano
发明人： Stephen J. Glica , Raymond L. Giordano
IPC分类号： H01L27/082 , H03K17/16 , H03K19/003
CPC分类号： H01L27/0821 , H03K17/16 , H03K19/00346
摘要： A first IGFET and a first bipolar transistor are connected in series between a first power terminaland a first load terminal. A second IGFET and a second bipolar transistor are connected in series between a second load terminal and a second power terminal. the first and second IGFETs are biased to pass the same load current. The first and second bipolar transistors are selectively turned on at the same time to permit current flow via a load which may be connected between the first and second terminals. When the first and second bipolar transistors are turned-off, they prevent conduction (except for leakage) between the load terminals and the first and second power terminals, if and when the voltage at the load terminal goes positive and/or negative. The circuit also includes means for compensating for the base current of the first and second bipolar transistors.
摘要翻译：第一IGFET和第一双极晶体管串联连接在第一功率端子和第一负载端子之间。第二IGFET和第二双极晶体管串联连接在第二负载端子和第二电源端子之间。第一和第二IGFET被偏置以通过相同的负载电流。第一和第二双极晶体管被选择性地同时导通，以允许电流通过可连接在第一和第二端子之间的负载流动。当第一和第二双极晶体管截止时，如果负载端子处的电压为正和/或负，则它们防止负载端子与第一和第二电源端子之间的导通（除了泄漏）。电路还包括用于补偿第一和第二双极晶体管的基极电流的装置。

6. 发明授权

US5130569A Power-on reset circuit 失效
标题翻译：上电复位电路
公开(公告)号：US5130569A
公开(公告)日：1992-07-14
申请号：US667932
申请日：1991-03-12
申请人： Stephen J. Glica
发明人： Stephen J. Glica
IPC分类号： G11C7/22 , G11C8/18 , H03K3/356 , H03K17/22
CPC分类号： G11C8/18 , G11C7/22 , H03K17/223 , H03K3/356008
摘要： A power-on reset circuit produces a momentary signal when the operating potential increases above a first threshold and when the operating potential decreases below a second threshold level. In a preferred embodiment, the circuit includes first and second IGFETs of first conductivity having their conduction paths connected in series between a positive operating terminal and a first node and third and fourth IGFETs of second conductivity having their conduction paths connected in series between the first node and a negative operating terminal. An inverter is connected at its input to the first node. The output of the inverter is coupled via a first feedback network to the intersection of the conduction paths of the third and fourth IGFETs to control the voltage level at which the third IGFET conducts when power ramps up. The output of the inverter is also coupled via a second feedback network to the intersection of the conduction paths of the first and second IGFETs to control the voltage level at which the second IGFET conducts when power ramps down.

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