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    • 1. 发明授权
    • Offset adjustment for fully differential amplifiers
    • 全差分放大器的偏移调整
    • US5736885A
    • 1998-04-07
    • US494395
    • 1995-06-26
    • Stanley Frank WietechaThomas D. HoustenJohn A. Olmstead
    • Stanley Frank WietechaThomas D. HoustenJohn A. Olmstead
    • H03F3/45
    • H03F3/45197H03F3/45744
    • A circuit for providing an input offset voltage to balance a fully differential amplifier may include two field effect transistors (FETs) in parallel conductive paths for receiving a current, an amplifier current source, a resistor connecting the FETs at their drains, and a second amplifier with inputs for an offset correction voltage and for a reference voltage on which the fully differential amplifier is to be balanced and outputs for providing control inputs to the FETs. The input offset voltage for balancing the fully differential amplifier is the difference between currents in the parallel paths times the resistance of the resistor. The circuit may be used to balance a fully differential amplifier in a telephone CODEC. The correction voltage may correct the total offset from the CODEC, or the offset introduced by a sign bit integrator that provides a correction for excursions of the same polarity in the CODEC.
    • 用于提供输入失调电压以平衡全差分放大器的电路可以包括用于接收电流的两个场效应晶体管(FET),用于接收电流,放大器电流源,在其漏极处连接FET的电阻器和第二放大器 具有用于偏移校正电压和用于平衡全差分放大器的参考电压的输入,以及用于向FET提供控制输入的输出。 用于平衡全差分放大器的输入失调电压是并联路径中的电流与电阻的电阻之差。 该电路可用于平衡电话CODEC中的全差分放大器。 校正电压可以校正来自CODEC的总偏移量,或由符号位积分器引入的补偿,其提供对CODEC中相同极性偏移的校正。
    • 2. 发明授权
    • Sign bit integrator and method
    • 符号位积分器和方法
    • US5617473A
    • 1997-04-01
    • US493454
    • 1995-06-23
    • Stanley F. WietechaJohn A. Olmstead
    • Stanley F. WietechaJohn A. Olmstead
    • H03M1/06H03M1/12H04M1/253H04M1/74H03M1/00H04M9/00
    • H04M1/253H03M1/0607H03M1/12
    • A sign bit integrator and method for generating a signal to correct an offset in a signal processing system that can distort the output from the system. A charge pulse is generated when the sign of a input signal is sampled in order to provide an offset correction signal with a polarity opposite that of offsets in the system. The charge pulse is provided to a pair of transistors whose size ratio sets the magnitude of the charge pulse. The polarity of the charge pulse is set responsive to a sign bit in the input signal. An integrator capacitor provides the offset correction signal to the signal processing system. A third transistor may be switchably substituted for one of the pair of transistors to change the ratio of sizes and thus change the magnitude of the charge pulse to thereby change the speed with which the offset correction is made. The sign bit integrator and method may be used to correct distortion in a voice signal in a telephone system.
    • 一种符号位积分器和方法,用于产生纠正信号处理系统中可能使系统输出失真的偏移的信号。 当对输入信号的符号进行采样时产生充电脉冲,以便提供具有与系统中的偏移极性相反极性的偏移校正信号。 充电脉冲被提供给一对晶体管,其尺寸比设定充电脉冲的幅度。 响应于输入信号中的符号位设置充电脉冲的极性。 积分器电容器向信号处理系统提供偏移校正信号。 第三晶体管可以切换地替代一对晶体管中的一个晶体管,以改变尺寸的比例,并因此改变充电脉冲的幅度,从而改变进行偏移校正的速度。 符号位积分器和方法可以用于校正电话系统中的语音信号中的失真。
    • 3. 发明授权
    • Amplifier with high common mode rejection
    • 具有高共模抑制功能的放大器
    • US5287071A
    • 1994-02-15
    • US980570
    • 1992-11-20
    • John A. OlmsteadSalomon Vulih
    • John A. OlmsteadSalomon Vulih
    • H03F3/45
    • H03F3/45183H03F3/45475H03F3/4565H03F2203/45002H03F2203/45466H03F2203/45476H03F2203/45612H03F2203/45658H03F2203/45711
    • A differential amplifier embodying the invention includes a differential stage whose total output current is sensed and whose "tail" and output current is maintained relatively constant over a large common mode voltage range by means of a current feedback loop. This feature eenables the differential amplifier to accurately amplify low amplitude signals riding on a very large common mode signal. The tail current to the differential amplifier is supplied by a controllable current source. The tail current flows via two differentially connected transistors in two differential output terminals and is divided between them as a function of the voltage applied to two differential signal input terminals. The amplitude of the tail current is set by a current level setting current source connected to a summing node. An amplifier and current mirroring network is connected between the summing node and the controllable current source. A current sensing and mirroring network is connected to the two differential outputs for sensing the total current flowing and feeding back a current proportional thereto to the summing node for maintaining the tail current relatively constant over wide variations in the voltage applied to the signal input terminals.
    • 实施本发明的差分放大器包括差分级,其感测总输出电流,并且通过电流反馈回路在“大”共模电压范围内“尾”和输出电流保持相对恒定。 该功能可使差分放大器精确放大乘坐非常大的共模信号的低幅度信号。 差分放大器的尾电流由可控电流源提供。 尾电流通过两个差分输出端子中的两个差分连接的晶体管流动,并根据施加到两个差分信号输入端子的电压进行分压。 尾电流的振幅由连接到求和节点的电流电平设置电流源设置。 放大器和电流镜像网络连接在求和节点和可控电流源之间。 电流检测和镜像网络连接到两个差分输出,用于感测总电流流动,并将与其成比例的电流反馈到求和节点,用于在施加到信号输入端子的电压的宽变化中保持尾电流相对恒定。
    • 5. 发明授权
    • Amplifier system for low level sensor signal
    • 用于低电平传感器信号的放大器系统
    • US5406223A
    • 1995-04-11
    • US979209
    • 1992-11-20
    • Salomon VulihJohn A. OlmsteadHarold A. Wittlinger
    • Salomon VulihJohn A. OlmsteadHarold A. Wittlinger
    • H03F3/45
    • H03F3/45645H03F3/45183H03F3/45475H03F3/4565H03F2203/45658H03F2203/45711
    • An amplifier system embodying the invention includes an input stage comprising one or more differential amplifiers having a high degree of common mode rejection. The inputs of the differential amplifiers of the input stage are AC coupled to different signal input terminals which are adapted to receive small information signals riding on large common mode signals. The AC coupling blocks any dc level associated with the input signals from affecting the amplifier system and the high degree of common mode rejection maintains the gain of the amplifiers relatively constant over a wide range of common mode signals. The outputs of the differential amplifiers of the input stage are connected in common to an output node to sum their output signals and to reduce random noise associated with the input signals and the input stage. The output node of the input stage is AC coupled to the input of a second stage whose output is in turn AC coupled to a third output stage to reduce the effect of amplifier offsets. The gain of the amplifier system is controlled by low pass filters connected to the output node of the input stage and to the output of the second stage. In certain embodiments a biasing clock is coupled via resistors to the inputs of the differential amplifiers to generate a dc bias level at their inputs which is a function of the duty cycle of the clock, the resistor connected at the input and coupling capacitor connected to the input.
    • 体现本发明的放大器系统包括输入级,该输入级包括具有高度共模抑制的一个或多个差分放大器。 输入级的差分放大器的输入端被AC耦合到不同的信号输入端子,这些信号输入端口适于接收乘以大型共模信号的小信息信号。 AC耦合阻止与输入信号相关联的任何直流电平影响放大器系统,高共模抑制保持放大器的增益在宽范围的共模信号上相对恒定。 输入级的差分放大器的输出共同连接到输出节点以对其输出信号求和,并减少与输入信号和输入级相关联的随机噪声。 输入级的输出节点被AC耦合到第二级的输入端,其输出又连接到第三输出级,以减小放大器偏移的影响。 放大器系统的增益由连接到输入级的输出节点和第二级输出的低通滤波器控制。 在某些实施例中,偏置时钟通过电阻器耦合到差分放大器的输入端,以在其输入端产生直流偏置电平,该偏置电平是时钟的占空比的函数,连接在输入端的电阻器和连接到 输入。
    • 7. 发明授权
    • Diode structure
    • 二极管结构
    • US4589002A
    • 1986-05-13
    • US631869
    • 1984-07-18
    • John A. Olmstead
    • John A. Olmstead
    • H01L29/06H01L29/866H01L29/90H01L29/91
    • H01L29/0688H01L29/866Y10S257/925
    • A diode structure is disclosed wherein the diode includes a body of a first type conductivity material; a first region of a second conductivity material in the body and having an opening therein through which a portion of the body projects; and a second region of the first conductivity material in the portion of the body that projects through the opening. The second region is rotationally positioned with respect to the first region so that it partially overlaps the first region at points of intersection of the two regions. These points of intersection are the rectifying junctions. The respective shapes of the opening and of the second region are arranged so that the sum of the areas of the breakdown junctions is a constant value notwithstanding that the second region may be displaced or misaligned with respect to the first region, provided that relative displacement or misalignment of the two regions is within defined limits.
    • 公开了二极管结构,其中二极管包括第一类导电材料的主体; 第二导电材料的第一区域,并且具有开口,身体的一部分穿过该开口突出; 以及在所述主体部分中穿过所述开口突出的所述第一导电材料的第二区域。 第二区域相对于第一区域旋转地定位,使得其在两个区域的交点处部分地与第一区域重叠。 这些交叉点是整流路口。 开口和第二区域的各个形状被布置成使得尽管第二区域可能相对于第一区域移位或不对准,但是击穿结的面积之和是恒定值,只要相对位移或 两个区域的不对准在限定的范围内。
    • 10. 发明授权
    • Comparator amplifier
    • 比较器放大器
    • US5287068A
    • 1994-02-15
    • US936596
    • 1992-08-27
    • John A. OlmsteadSalomon Vulih
    • John A. OlmsteadSalomon Vulih
    • H03F1/08H03K5/24H03F1/02H03F3/45
    • H03K5/249H03F1/086H03K5/2481
    • An amplifier includes first and second amplifying stages with the first amplifying stage having an inverting input, a non-inverting input and an intermediate output node at which is produced a signal responsive to signals applied to the inverting and non-inverting inputs. The second amplifying stage has an input connected to the intermediate output node and an output connected to an amplifier output terminal. A selectively enabled transmission gate is connected in series with a capacitor between the input and the output of the second amplifying stage. The selectively enabled transmission gate means, when enabled, functions as a resistance which in combination with the capacitor provides frequency compensation for the amplifier. When the transmission gate is disabled, it functions to disconnect one side of the capacitor and eliminates its loading effect on the amplifier stage.
    • 放大器包括第一和第二放大级,其中第一放大级具有反相输入,非反相输入和中间输出节点,其中响应于施加到反相和非反相输入的信号产生信号。 第二放大级具有连接到中间输出节点的输入端和连接到放大器输出端子的输出。 选择使能的传输门与第二放大级的输入和输出之间的电容器串联连接。 选择使能的传输门装置在使能时用作与电容器组合提供放大器的频率补偿的电阻。 当传输门禁用时,它可以断开电容器的一侧,并消除其在放大器级上的负载效应。