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1. 发明授权

US06552381B2 Trench capacitors in SOI substrates 有权
标题翻译： SOI衬底中的沟槽电容器
公开(公告)号：US06552381B2
公开(公告)日：2003-04-22
申请号：US10072500
申请日：2002-02-05
申请人： Sailesh Chittipeddi , Charles Walter Pearce , Pradip Kumar Roy
发明人： Sailesh Chittipeddi , Charles Walter Pearce , Pradip Kumar Roy
IPC分类号： H01L27108
CPC分类号： H01L29/66181 , H01L27/1203 , H01L29/945
摘要： A trench capacitor formed on an SOI substrate extends through an upper silicon layer and an insulating layer and into a semiconductor base substrate. The outer electrode of the trench capacitor includes portions of the semiconductor base substrate which bound the trench in which the trench capacitor is formed. The outer electrode is coupled to a contact structure formed in close proximity to the trench capacitor, and which extends through the insulating layer. The method for simultaneously producing the trench capacitor and contact structure includes forming two trench openings, forming a dielectric liner on one of the trench openings, then filling each of the trench openings with a semiconductor material.
摘要翻译：形成在SOI衬底上的沟槽电容器延伸穿过上硅层和绝缘层并进入半导体基底衬底。沟槽电容器的外部电极包括半导体基底基板的限定形成沟槽电容器的沟槽的部分。外电极耦合到紧邻沟槽电容器形成的接触结构，并延伸穿过绝缘层。用于同时制造沟槽电容器和接触结构的方法包括形成两个沟槽开口，在一个沟槽开口上形成电介质衬垫，然后用半导体材料填充每个沟槽开口。

2. 发明授权

US06387772B1 Method for forming trench capacitors in SOI substrates 有权
标题翻译：在SOI衬底中形成沟槽电容器的方法
公开(公告)号：US06387772B1
公开(公告)日：2002-05-14
申请号：US09557536
申请日：2000-04-25
申请人： Sailesh Chittipeddi , Charles Walter Pearce , Pradip Kumar Roy
发明人： Sailesh Chittipeddi , Charles Walter Pearce , Pradip Kumar Roy
IPC分类号： H01L2120
CPC分类号： H01L29/66181 , H01L27/1203 , H01L29/945
摘要： A trench capacitor formed on an SOI substrate extends through an upper silicon layer and an insulating layer and into a semiconductor base substrate. The outer electrode of the trench capacitor includes portions of the semiconductor base substrate which bound the trench in which the trench capacitor is formed. The outer electrode is coupled to a contact structure formed in close proximity to the trench capacitor, and which extends through the insulating layer. The method for simultaneously producing the trench capacitor and contact structure includes forming two trench openings, forming a dielectric liner on one of the trench openings, then filling each of the trench openings with a semiconductor material.
摘要翻译：形成在SOI衬底上的沟槽电容器延伸穿过上硅层和绝缘层并进入半导体基底衬底。沟槽电容器的外部电极包括半导体基底基板的限定形成沟槽电容器的沟槽的部分。外电极耦合到紧邻沟槽电容器形成的接触结构，并延伸穿过绝缘层。用于同时制造沟槽电容器和接触结构的方法包括形成两个沟槽开口，在一个沟槽开口上形成电介质衬垫，然后用半导体材料填充每个沟槽开口。

3. 发明授权

US06319837B1 Technique for reducing dishing in Cu-based interconnects 有权
标题翻译：减少铜基互连中凹陷的技术
公开(公告)号：US06319837B1
公开(公告)日：2001-11-20
申请号：US09606833
申请日：2000-06-29
申请人： Sailesh Chittipeddi , Sailesh Mansinh Merchant , Pradip Kumar Roy
发明人： Sailesh Chittipeddi , Sailesh Mansinh Merchant , Pradip Kumar Roy
IPC分类号： H01L2100
CPC分类号： H01L21/7684
摘要： The present invention includes a method for reducing dishing of an integrated circuit interconnect, comprising the steps of providing excess interconnect material above a damascene feature in a substrate and planarizing the substrate and interconnect material to obtain an interconnect in the substrate.
摘要翻译：本发明包括一种用于减少集成电路互连的凹陷的方法，包括以下步骤：在衬底上的镶嵌特征之上提供过量的互连材料，并平坦化衬底和互连材料以获得衬底中的互连。

4. 发明授权

US06482694B2 Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers 有权
标题翻译：包括夹在氮化硅层之间的五氧化二钽层的半导体器件结构
公开(公告)号：US06482694B2
公开(公告)日：2002-11-19
申请号：US09878657
申请日：2001-06-11
申请人： Sailesh Chittipeddi , Charles Walter Pearce
发明人： Sailesh Chittipeddi , Charles Walter Pearce
IPC分类号： H01L218242
CPC分类号： H01L28/40 , H01L21/3144 , H01L21/31604 , H01L21/3185 , H01L27/0805 , H01L27/1085
摘要： An insulating structure includes a first silicon nitride layer, a tantalum pentoxide layer formed above the first silicon nitride (SiNx) layer, and a second silicon nitride layer formed above the tantalum pentoxide (Ta2O5) layer. The SiNx cladding layers prevent diffusion of the tantalum during heating. A high dielectric constant is provided. The thermal stability of the insulating structure is improved. The insulating structure may be included in a capacitor or a shallow trench isolation structure. An exemplary capacitor is formed with a substrate, a lower electrode, the three-layer SixNy/Ta2O5/SixNy structure and an upper electrode. The lower electrode may include a TiN layer formed over an aluminum layer, or a TiN layer formed over a polysilicon layer, or a polysilicon layer having an oxide barrier layer formed on it. The upper electrode may be a TiN layer or a polysilicon layer. An exemplary shallow trench isolation structure includes the SixNy/Ta2O5/SixNy structure as a liner on the sides and bottom of a shallow trench in the surface of a substrate. The shallow trench is filled with an oxide, such as TEOS. A variety of methods may be used for fabricating devices that include the SixNy/Ta2O5/SixNy structure.
摘要翻译：绝缘结构包括第一氮化硅层，形成在第一氮化硅（SiNx）层上方的五氧化二钽层和形成在五氧化二钽（Ta2O5）上方的第二氮化硅层。 SiNx覆层在加热期间防止钽的扩散。提供高介电常数。绝缘结构的热稳定性提高。绝缘结构可以包括在电容器或浅沟槽隔离结构中。示例性电容器由基板，下电极，三层SixNy / Ta2O5 / SixNy结构和上电极形成。下电极可以包括在铝层上形成的TiN层，或者形成在多晶硅层上的TiN层，或者在其上形成有氧化物阻挡层的多晶硅层。上电极可以是TiN层或多晶硅层。示例性的浅沟槽隔离结构包括作为衬底在衬底表面的浅沟槽的侧面和底部上的SixNy / Ta2O5 / SixNy结构。浅沟槽中填充有氧化物，如TEOS。可以使用各种方法来制造包括SixNy / Ta2O5 / SixNy结构的器件。

5. 发明授权

US06294807B1 Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers 有权
标题翻译：包括夹在氮化硅层之间的五氧化二钽层的半导体器件结构
公开(公告)号：US06294807B1
公开(公告)日：2001-09-25
申请号：US09259001
申请日：1999-02-26
申请人： Sailesh Chittipeddi , Charles Walter Pearce
发明人： Sailesh Chittipeddi , Charles Walter Pearce
IPC分类号： H01L27108
CPC分类号： H01L28/40 , H01L21/3144 , H01L21/31604 , H01L21/3185 , H01L27/0805 , H01L27/1085
摘要： An insulating structure includes a first silicon nitride layer, a tantalum pentoxide layer formed above the first silicon nitride (SiNx) layer, and a second silicon nitride layer formed above the tantalum pentoxide (Ta2O5) layer. The SiNx cladding layers prevent difflusion of the tantalum during heating. A high dielectric constant is provided. The thermal stability of the insulating structure is improved. The insulating structure may be included in a capacitor or a shallow trench isolation structure. An exemplary capacitor is formed with a substrate, a lower electrode, the three-layer SixNy/Ta2O5/SixNy structure and an upper electrode. The lower electrode may include a TiN layer formed over an aluminum layer, or a TiN layer formed over a polysilicon layer, or a polysilicon layer having an oxide barrier layer formed on it. The upper electrode may be a TiN layer or a polysilicon layer. An exemplary shallow trench isolation structure includes the SixNy/Ta2O5/SixNy structure as a liner on the sides and bottom of a shallow trench in the surface of a substrate. The shallow trench is filled with an oxide, such as TEOS. A variety of methods may be used for fabricating devices that include the SixNy/Ta2O5/SixNy structure.
摘要翻译：绝缘结构包括第一氮化硅层，形成在第一氮化硅（SiNx）层上方的五氧化二钽层和形成在五氧化二钽（Ta2O5）上方的第二氮化硅层。 SiNx覆层在加热期间防止了钽的杂散。提供高介电常数。绝缘结构的热稳定性提高。绝缘结构可以包括在电容器或浅沟槽隔离结构中。示例性电容器由基板，下电极，三层SixNy / Ta2O5 / SixNy结构和上电极形成。下电极可以包括在铝层上形成的TiN层，或者形成在多晶硅层上的TiN层，或者在其上形成有氧化物阻挡层的多晶硅层。上电极可以是TiN层或多晶硅层。示例性的浅沟槽隔离结构包括作为衬底在衬底表面的浅沟槽的侧面和底部上的SixNy / Ta2O5 / SixNy结构。浅沟槽中填充有氧化物，如TEOS。可以使用各种方法来制造包括SixNy / Ta2O5 / SixNy结构的器件。

6. 发明授权

US06838769B1 Dual damascene bond pad structure for lowering stress and allowing circuitry under pads 有权
标题翻译：双镶嵌结合垫结构，用于降低压力并允许垫下的电路
公开(公告)号：US06838769B1
公开(公告)日：2005-01-04
申请号：US09465089
申请日：1999-12-16
申请人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
发明人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
IPC分类号： H01L21/60 , H01L21/768 , H01L23/485 , H01L23/532 , H01L29/40 , H01L23/52
CPC分类号： H01L24/48 , H01L21/76807 , H01L23/53209 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/04042 , H01L2224/05093 , H01L2224/05096 , H01L2224/05166 , H01L2224/05187 , H01L2224/05546 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： A bond pad is located over active circuitry formed within an integrated circuit device. A barrier film forms the bottom surface of the upper portion of a bond pad opening which also includes vias extending through the bottom surface to form a dual damascene structure. The bond pad is resistant to stress effects such as cracking, which can be produced when bonding an external wire to the bond pad, and therefore prevents leakage currents between the bond pads and the underlying circuitry.
摘要翻译：接合焊盘位于集成电路器件内形成的有源电路上。阻挡膜形成接合焊盘开口的上部的底表面，其还包括延伸穿过底表面的通孔以形成双镶嵌结构。接合焊盘抵抗诸如开裂的应力作用，当将外部导线接合到接合焊盘时可以产生裂纹，因此防止接合焊盘和下面的电路之间的漏电流。

7. 发明授权

US06628001B1 Integrated circuit die having alignment marks in the bond pad region and method of manufacturing same 有权
标题翻译：具有接合焊盘区域中的对准标记的集成电路管芯及其制造方法
公开(公告)号：US06628001B1
公开(公告)日：2003-09-30
申请号：US10150790
申请日：2002-05-17
申请人： Sailesh Chittipeddi , Keelathur N. Vasudevan
发明人： Sailesh Chittipeddi , Keelathur N. Vasudevan
IPC分类号： H01L23544
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a die located on a semiconductor wafer. In one embodiment, the die includes a circuit region located within a circuit perimeter of the die. In addition, the die includes a bond pad region located between the circuit perimeter and an outer perimeter of the die. Also the die includes an alignment mark located within the bond pad region.
摘要翻译：本发明提供一种位于半导体晶片上的裸片。在一个实施例中，管芯包括位于管芯的电路周边内的电路区域。此外，管芯包括位于电路周边和管芯的外周边之间的接合焊盘区域。此外，管芯包括位于接合焊盘区域内的对准标记。

8. 发明授权

US06538283B1 Silicon-on-insulator (SOI) semiconductor structure with additional trench including a conductive layer 有权
标题翻译：绝缘体上硅（SOI）半导体结构，具有包括导电层的附加沟槽
公开(公告)号：US06538283B1
公开(公告)日：2003-03-25
申请号：US09611907
申请日：2000-07-07
申请人： Sailesh Chittipeddi , Michael J. Kelly
发明人： Sailesh Chittipeddi , Michael J. Kelly
IPC分类号： H01L2701
CPC分类号： H01L29/66181 , H01L21/7624 , H01L21/84 , H01L27/0805 , H01L27/1203
摘要： A semiconductor device comprising a silicon-on-insulator (SOI) substrate including a base substrate, an insulator layer, and a silicon layer, and a trench capacitor including at least one trench formed in the silicon-on-insulator substrate and extending through the base substrate, the insulator layer and the silicon layer, wherein the at least one trench includes at least one layer of silicon dioxide formed therein. In a preferred embodiment, semiconductor material disposed in the at least one trench forms a first electrode of a semiconductor capacitor, and semiconductor material of the SOI substrate which lies adjacent to the at least one trench forms a second electrode of the capacitor.
摘要翻译：一种包括绝缘体上硅（SOI）衬底的半导体器件，包括基底衬底，绝缘体层和硅层，以及沟槽电容器，其包括形成在绝缘体上硅衬底中的至少一个沟槽，基底衬底，绝缘体层和硅层，其中至少一个沟槽包括在其中形成的至少一层二氧化硅。在优选实施例中，设置在至少一个沟槽中的半导体材料形成半导体电容器的第一电极，并且位于与至少一个沟槽相邻的SOI衬底的半导体材料形成电容器的第二电极。

9. 发明授权

US06498080B1 Transistor fabrication method 失效
标题翻译：晶体管制造方法
公开(公告)号：US06498080B1
公开(公告)日：2002-12-24
申请号：US08587061
申请日：1996-01-16
申请人： Sailesh Chittipeddi , Taeho Kook , Avinoam Kornblit
发明人： Sailesh Chittipeddi , Taeho Kook , Avinoam Kornblit
IPC分类号： H01L213205
CPC分类号： H01L29/66575 , H01L21/0276 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.
摘要翻译：公开了一种形成集成电路中没有通道的可控线宽的低堆叠高度晶体管的方法。使用掺杂玻璃的一次性硬掩模来限定栅极并且随后在形成源极和漏极的离子注入期间保护栅极（和下面的衬底）。可以形成各种硅化和非硅化的结构。

10. 发明授权

US06417087B1 Process for forming a dual damascene bond pad structure over active circuitry 有权
标题翻译：用于在有源电路上形成双镶嵌键合焊盘结构的工艺
公开(公告)号：US06417087B1
公开(公告)日：2002-07-09
申请号：US09465075
申请日：1999-12-16
申请人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
发明人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
IPC分类号： H01L2144
CPC分类号： H01L24/48 , H01L21/76807 , H01L23/53209 , H01L24/05 , H01L24/11 , H01L2221/1036 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05546 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： A process for forming a dual damascene bond pad within an integrated circuit produces a bond pad which is resistant to stress effects and which therefore allows for the bond pad to be formed over active circuitry. The process includes forming a dual damascene structure by forming a bond pad opening having a barrier layer film on the bottom surface of the upper portion of the opening, and forming vias which extend downwardly through the bottom surface. The process produces a bond pad which is resistant to stress effects such as cracking which can be produced when bonding an external wire to the bond pad. Leakage currents between the bond pad and the underlying circuitry are prevented.
摘要翻译：用于在集成电路内形成双镶嵌键合焊盘的工艺产生接合焊盘，其抵抗应力作用并因此允许在有源电路上形成接合焊盘。该方法包括通过在开口的上部的底部表面上形成具有阻挡层膜的接合焊盘开口形成双镶嵌结构，以及形成向下延伸通过底表面的通孔。该工艺产生接合焊盘，其抵抗诸如当将外部电线接合到接合焊盘时可产生的应力作用的破坏。防止接合焊盘和底层电路之间的泄漏电流。

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