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1. 发明授权

US06387772B1 Method for forming trench capacitors in SOI substrates 有权
标题翻译：在SOI衬底中形成沟槽电容器的方法
公开(公告)号：US06387772B1
公开(公告)日：2002-05-14
申请号：US09557536
申请日：2000-04-25
申请人： Sailesh Chittipeddi , Charles Walter Pearce , Pradip Kumar Roy
发明人： Sailesh Chittipeddi , Charles Walter Pearce , Pradip Kumar Roy
IPC分类号： H01L2120
CPC分类号： H01L29/66181 , H01L27/1203 , H01L29/945
摘要： A trench capacitor formed on an SOI substrate extends through an upper silicon layer and an insulating layer and into a semiconductor base substrate. The outer electrode of the trench capacitor includes portions of the semiconductor base substrate which bound the trench in which the trench capacitor is formed. The outer electrode is coupled to a contact structure formed in close proximity to the trench capacitor, and which extends through the insulating layer. The method for simultaneously producing the trench capacitor and contact structure includes forming two trench openings, forming a dielectric liner on one of the trench openings, then filling each of the trench openings with a semiconductor material.
摘要翻译：形成在SOI衬底上的沟槽电容器延伸穿过上硅层和绝缘层并进入半导体基底衬底。沟槽电容器的外部电极包括半导体基底基板的限定形成沟槽电容器的沟槽的部分。外电极耦合到紧邻沟槽电容器形成的接触结构，并延伸穿过绝缘层。用于同时制造沟槽电容器和接触结构的方法包括形成两个沟槽开口，在一个沟槽开口上形成电介质衬垫，然后用半导体材料填充每个沟槽开口。

2. 发明授权

US06552381B2 Trench capacitors in SOI substrates 有权
标题翻译： SOI衬底中的沟槽电容器
公开(公告)号：US06552381B2
公开(公告)日：2003-04-22
申请号：US10072500
申请日：2002-02-05
申请人： Sailesh Chittipeddi , Charles Walter Pearce , Pradip Kumar Roy
发明人： Sailesh Chittipeddi , Charles Walter Pearce , Pradip Kumar Roy
IPC分类号： H01L27108
CPC分类号： H01L29/66181 , H01L27/1203 , H01L29/945
摘要： A trench capacitor formed on an SOI substrate extends through an upper silicon layer and an insulating layer and into a semiconductor base substrate. The outer electrode of the trench capacitor includes portions of the semiconductor base substrate which bound the trench in which the trench capacitor is formed. The outer electrode is coupled to a contact structure formed in close proximity to the trench capacitor, and which extends through the insulating layer. The method for simultaneously producing the trench capacitor and contact structure includes forming two trench openings, forming a dielectric liner on one of the trench openings, then filling each of the trench openings with a semiconductor material.
摘要翻译：形成在SOI衬底上的沟槽电容器延伸穿过上硅层和绝缘层并进入半导体基底衬底。沟槽电容器的外部电极包括半导体基底基板的限定形成沟槽电容器的沟槽的部分。外电极耦合到紧邻沟槽电容器形成的接触结构，并延伸穿过绝缘层。用于同时制造沟槽电容器和接触结构的方法包括形成两个沟槽开口，在一个沟槽开口上形成电介质衬垫，然后用半导体材料填充每个沟槽开口。

3. 发明授权

US06482694B2 Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers 有权
标题翻译：包括夹在氮化硅层之间的五氧化二钽层的半导体器件结构
公开(公告)号：US06482694B2
公开(公告)日：2002-11-19
申请号：US09878657
申请日：2001-06-11
申请人： Sailesh Chittipeddi , Charles Walter Pearce
发明人： Sailesh Chittipeddi , Charles Walter Pearce
IPC分类号： H01L218242
CPC分类号： H01L28/40 , H01L21/3144 , H01L21/31604 , H01L21/3185 , H01L27/0805 , H01L27/1085
摘要： An insulating structure includes a first silicon nitride layer, a tantalum pentoxide layer formed above the first silicon nitride (SiNx) layer, and a second silicon nitride layer formed above the tantalum pentoxide (Ta2O5) layer. The SiNx cladding layers prevent diffusion of the tantalum during heating. A high dielectric constant is provided. The thermal stability of the insulating structure is improved. The insulating structure may be included in a capacitor or a shallow trench isolation structure. An exemplary capacitor is formed with a substrate, a lower electrode, the three-layer SixNy/Ta2O5/SixNy structure and an upper electrode. The lower electrode may include a TiN layer formed over an aluminum layer, or a TiN layer formed over a polysilicon layer, or a polysilicon layer having an oxide barrier layer formed on it. The upper electrode may be a TiN layer or a polysilicon layer. An exemplary shallow trench isolation structure includes the SixNy/Ta2O5/SixNy structure as a liner on the sides and bottom of a shallow trench in the surface of a substrate. The shallow trench is filled with an oxide, such as TEOS. A variety of methods may be used for fabricating devices that include the SixNy/Ta2O5/SixNy structure.
摘要翻译：绝缘结构包括第一氮化硅层，形成在第一氮化硅（SiNx）层上方的五氧化二钽层和形成在五氧化二钽（Ta2O5）上方的第二氮化硅层。 SiNx覆层在加热期间防止钽的扩散。提供高介电常数。绝缘结构的热稳定性提高。绝缘结构可以包括在电容器或浅沟槽隔离结构中。示例性电容器由基板，下电极，三层SixNy / Ta2O5 / SixNy结构和上电极形成。下电极可以包括在铝层上形成的TiN层，或者形成在多晶硅层上的TiN层，或者在其上形成有氧化物阻挡层的多晶硅层。上电极可以是TiN层或多晶硅层。示例性的浅沟槽隔离结构包括作为衬底在衬底表面的浅沟槽的侧面和底部上的SixNy / Ta2O5 / SixNy结构。浅沟槽中填充有氧化物，如TEOS。可以使用各种方法来制造包括SixNy / Ta2O5 / SixNy结构的器件。

4. 发明授权

US06294807B1 Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers 有权
标题翻译：包括夹在氮化硅层之间的五氧化二钽层的半导体器件结构
公开(公告)号：US06294807B1
公开(公告)日：2001-09-25
申请号：US09259001
申请日：1999-02-26
申请人： Sailesh Chittipeddi , Charles Walter Pearce
发明人： Sailesh Chittipeddi , Charles Walter Pearce
IPC分类号： H01L27108
CPC分类号： H01L28/40 , H01L21/3144 , H01L21/31604 , H01L21/3185 , H01L27/0805 , H01L27/1085
摘要： An insulating structure includes a first silicon nitride layer, a tantalum pentoxide layer formed above the first silicon nitride (SiNx) layer, and a second silicon nitride layer formed above the tantalum pentoxide (Ta2O5) layer. The SiNx cladding layers prevent difflusion of the tantalum during heating. A high dielectric constant is provided. The thermal stability of the insulating structure is improved. The insulating structure may be included in a capacitor or a shallow trench isolation structure. An exemplary capacitor is formed with a substrate, a lower electrode, the three-layer SixNy/Ta2O5/SixNy structure and an upper electrode. The lower electrode may include a TiN layer formed over an aluminum layer, or a TiN layer formed over a polysilicon layer, or a polysilicon layer having an oxide barrier layer formed on it. The upper electrode may be a TiN layer or a polysilicon layer. An exemplary shallow trench isolation structure includes the SixNy/Ta2O5/SixNy structure as a liner on the sides and bottom of a shallow trench in the surface of a substrate. The shallow trench is filled with an oxide, such as TEOS. A variety of methods may be used for fabricating devices that include the SixNy/Ta2O5/SixNy structure.
摘要翻译：绝缘结构包括第一氮化硅层，形成在第一氮化硅（SiNx）层上方的五氧化二钽层和形成在五氧化二钽（Ta2O5）上方的第二氮化硅层。 SiNx覆层在加热期间防止了钽的杂散。提供高介电常数。绝缘结构的热稳定性提高。绝缘结构可以包括在电容器或浅沟槽隔离结构中。示例性电容器由基板，下电极，三层SixNy / Ta2O5 / SixNy结构和上电极形成。下电极可以包括在铝层上形成的TiN层，或者形成在多晶硅层上的TiN层，或者在其上形成有氧化物阻挡层的多晶硅层。上电极可以是TiN层或多晶硅层。示例性的浅沟槽隔离结构包括作为衬底在衬底表面的浅沟槽的侧面和底部上的SixNy / Ta2O5 / SixNy结构。浅沟槽中填充有氧化物，如TEOS。可以使用各种方法来制造包括SixNy / Ta2O5 / SixNy结构的器件。

5. 发明申请

US20090267145A1 MOSFET DEVICE HAVING DUAL INTERLEVEL DIELECTRIC THICKNESS AND METHOD OF MAKING SAME 审中-公开
标题翻译：具有双重交互电导厚度的MOSFET器件及其制造方法
公开(公告)号：US20090267145A1
公开(公告)日：2009-10-29
申请号：US12108045
申请日：2008-04-23
申请人： Charles Walter Pearce , Simon J. Molloy , Shuming Xu , Xiao Rui Li
发明人： Charles Walter Pearce , Simon J. Molloy , Shuming Xu , Xiao Rui Li
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/402 , H01L29/66659 , H01L29/7835
摘要： A method of forming a metal-oxide-semiconductor (MOS) device includes the following steps: forming a semiconductor layer of a first conductivity type having source and drain regions of a second conductivity type, a channel region and a lightly-doped drain region formed therein; forming a gate over the channel region proximate an upper surface of the semiconductor layer; after the forming steps, depositing a first dielectric layer having a first thickness over an upper surface of the semiconductor layer; etching the first dielectric layer in a region over the lightly-doped drain proximate to the gate to reduce its thickness; conformably depositing a second dielectric layer having a second thickness over the first dielectric layer, including in the etched region, the second thickness being less than the first thickness; and forming a shielding electrode over the second dielectric layer.
摘要翻译：形成金属氧化物半导体（MOS）器件的方法包括以下步骤：形成第一导电类型的半导体层，其具有第二导电类型的源极和漏极区域，沟道区域和形成的轻掺杂漏极区域其中在靠近半导体层的上表面的沟道区上形成栅极; 在形成步骤之后，在半导体层的上表面上沉积具有第一厚度的第一介电层; 在靠近栅极的轻掺杂漏极上的区域中蚀刻第一介电层以减小其厚度; 在所述第一介电层上沉积具有第二厚度的第二介电层，所述第二介电层包括在所述蚀刻区域中，所述第二厚度小于所述第一厚度; 以及在所述第二电介质层上形成屏蔽电极。

6. 发明授权

US06762457B2 LDMOS device having a tapered oxide 有权
标题翻译： LDMOS器件具有锥形氧化物
公开(公告)号：US06762457B2
公开(公告)日：2004-07-13
申请号：US10300254
申请日：2002-11-20
申请人： Charles Walter Pearce , Muhammed Ayman Shibib
发明人： Charles Walter Pearce , Muhammed Ayman Shibib
IPC分类号： H01L2976
CPC分类号： H01L29/7816 , H01L21/32 , H01L21/76202 , H01L29/0878 , H01L29/42368
摘要： The invention includes a laterally diffused metal oxide semiconductor transistor comprising a gate electrode and comprising tapered oxide self aligned to the gate electrode.
摘要翻译：本发明包括横向扩散的金属氧化物半导体晶体管，其包括栅电极并且包括与栅电极自对准的锥形氧化物。

7. 发明授权

US06245692B1 Method to selectively heat semiconductor wafers 有权
标题翻译：选择性加热半导体晶片的方法
公开(公告)号：US06245692B1
公开(公告)日：2001-06-12
申请号：US09448349
申请日：1999-11-23
申请人： Charles Walter Pearce , Michael Steven Billig
发明人： Charles Walter Pearce , Michael Steven Billig
IPC分类号： H01L2126
CPC分类号： H01L29/665 , H01L21/324
摘要： A method for manufacturing integrated circuits; particularly, a method to alter heat flow on a localized basis, when heating wafers to elevated temperatures, to achieve different processing temperatures by altering the material properties, such as emissivity, absorptivity and reflectivity, of a portion of a surface by the application of thin films of various materials.
摘要翻译：一种制造集成电路的方法; 特别地，当将晶片加热到升高的温度时，通过改变表面的一部分的材料性质（如发射率，吸收率和反射率）来实现不同的加工温度，从而在局部基础上改变热流。各种材料的电影。

8. 发明授权

US06361614B1 Dark spin rinse/dry 有权
标题翻译：黑暗旋转冲洗/干燥
公开(公告)号：US06361614B1
公开(公告)日：2002-03-26
申请号：US09510015
申请日：2000-02-22
申请人： Bryan Chaeyoo Chung , Glenn Alan Marshall , Charles Walter Pearce , Kevin Paul Yanders
发明人： Bryan Chaeyoo Chung , Glenn Alan Marshall , Charles Walter Pearce , Kevin Paul Yanders
IPC分类号： C23G102
CPC分类号： H01L21/67057 , B08B3/00 , Y10S134/902
摘要： A method and apparatus for eliminating the exposure of semiconductor wafers to light during rinsing and drying in wafer cleaning machines having windows is used to reduce scrap and improve the reliability of the integrated circuit devices. An opaque window assembly or a light blocking material is applied to the transparent window to prevent ambient light from entering the processing chamber of the wafer cleaning machine and thereby eliminate light-induced galvanic corrosion produced during rinsing and drying of semiconductor wafers in wafer cleaning machines having windows. This makes the fabrication of advanced integrated circuit devices of increasingly smaller dimensions feasible by eliminating the degradation in reliability caused by light-induced galvanic corrosion produced during cleaning of the semiconductor wafers. The application of a light blocking material to the transparent windows of wafer cleaning machine is cost effective and easily implemented in existing wafer cleaning machines.
摘要翻译：用于在具有窗户的晶片清洁机中清洗和干燥期间消除半导体晶片曝光的方法和装置用于减少废料并提高集成电路器件的可靠性。将不透明窗组件或遮光材料施加到透明窗口以防止环境光进入晶片清洁机的处理室，从而消除在晶片清洗机中的半导体晶片的漂洗和干燥过程中产生的光诱导的电偶腐蚀，视窗。这使得通过消除在半导体晶片的清洁期间产生的光诱导的电偶腐蚀导致的可靠性降低，使得尺寸越来越小的先进集成电路器件的制造变得可行。将光阻材料应用于晶圆清洗机的透明窗口是经济有效的并且容易在现有的晶圆清洗机中实现。

9. 发明授权

US06358865B2 Oxidation of silicon using fluorine implant 有权
标题翻译：使用氟植入物氧化硅
公开(公告)号：US06358865B2
公开(公告)日：2002-03-19
申请号：US09311631
申请日：1999-05-14
申请人： Charles Walter Pearce , Daniel Joseph McKee , Jeffrey Kenneth Haas
发明人： Charles Walter Pearce , Daniel Joseph McKee , Jeffrey Kenneth Haas
IPC分类号： H01L2131
CPC分类号： H01L21/76213 , H01L21/26506 , H01L21/823462 , H01L21/823481 , Y10S438/981
摘要： A method is disclosed for the oxidation of a substrate and the formation of oxide regions in the substrate by implantation of fluorine into the silicon lattice and subsequently forming an oxide region by a typical oxide growth process. The oxide growth process may be those such as thermal oxidation or the local oxidation of silicon. The process according to the present invention allows for the simultaneous growth of oxides having different thicknesses at the same time by tailoring the fluorine implantation.
摘要翻译：公开了一种用于氧化衬底和通过将氟注入到硅晶格中并随后通过典型的氧化物生长工艺形成氧化物区域而在衬底中形成氧化物区域的方法。氧化物生长过程可以是诸如热氧化或硅的局部氧化的过程。根据本发明的方法允许通过调整氟注入同时生长具有不同厚度的氧化物。

10. 发明授权

US08294210B2 High voltage channel diode 有权
标题翻译：高压通道二极管
公开(公告)号：US08294210B2
公开(公告)日：2012-10-23
申请号：US12815877
申请日：2010-06-15
申请人： Christopher Boguslaw Kocon , John Manning Savidge Neilson , Simon John Molloy , Haian Lin , Charles Walter Pearce , Gary Eugene Daum
发明人： Christopher Boguslaw Kocon , John Manning Savidge Neilson , Simon John Molloy , Haian Lin , Charles Walter Pearce , Gary Eugene Daum
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L29/861 , H01L29/402 , H01L29/6609 , H01L29/7835
摘要： A channel diode structure having a drift region and method of forming. A charge balanced channel diode structure having an electrode shield and method of forming.
摘要翻译：具有漂移区域和形成方法的沟道二极管结构。具有电极屏蔽的电荷平衡沟道二极管结构和形成方法。

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