专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120198396A1 METHOD OF OPTIMIZING SEMICONDUCTOR DEVICE MANUFACTURING PROCESS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND NON-TRANSITORY COMPUTER READABLE MEDIUM 审中-公开
标题翻译：优化半导体器件制造工艺的方法，制造半导体器件的方法和非电子计算机可读介质
公开(公告)号：US20120198396A1
公开(公告)日：2012-08-02
申请号：US13237854
申请日：2011-09-20
申请人： Masanari KAJIWARA , Sachiko Kobayashi , Satoshi Tanaka , Kazuhiro Takahata , Shigeki Nojima , Toshiya Kotani , Shimon Maeda
发明人： Masanari KAJIWARA , Sachiko Kobayashi , Satoshi Tanaka , Kazuhiro Takahata , Shigeki Nojima , Toshiya Kotani , Shimon Maeda
IPC分类号： G06F17/50
CPC分类号： H01L22/20 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A method of optimizing a semiconductor device manufacturing process according to an embodiment is a method of optimizing a semiconductor device manufacturing process in which a pattern based on circuit design is formed. The method of optimizing a semiconductor device manufacturing process according to the embodiment includes: at the time of calculation of a statistic amount based on a distribution of differences at a plurality of sites between a pattern formed by a first exposing apparatus in a first condition and a pattern formed by a second exposing apparatus in a second condition, calculating the statistic amount after applying weighting to the differences based on information on an electrical characteristic; and repeating the calculating with the second condition being changed, and selecting an condition in which the total sum becomes a minimum or equal to or less than a standard value as an optimized condition of the second exposing apparatus.
摘要翻译：根据实施例的优化半导体器件制造工艺的方法是优化其中形成基于电路设计的图案的半导体器件制造工艺的方法。根据实施例的半导体器件制造方法的优化方法包括：在基于在第一状态下由第一曝光装置形成的图案与第一状态之间的多个位置处的差异的分布的统计量的计算时，在第二状态下由第二曝光装置形成的图案，基于关于电特性的信息对所述差进行加权计算后的统计量; 并重复进行第二条件的计算，并且选择总和变为最小或等于或小于标准值的条件作为第二曝光装置的优化条件。

2. 发明申请

US20050251781A1 Design pattern correcting method, design pattern forming method, process proximity effect correcting method, semiconductor device and design pattern correcting program 审中-公开
标题翻译：设计模式校正方法，设计模式形成方法，过程接近效应校正方法，半导体器件和设计模式校正程序
公开(公告)号：US20050251781A1
公开(公告)日：2005-11-10
申请号：US11115322
申请日：2005-04-27
申请人： Toshiya Kotani , Shigeki Nojima , Shimon Maeda
发明人： Toshiya Kotani , Shigeki Nojima , Shimon Maeda
IPC分类号： G03C5/00 , G03F1/36 , G03F1/68 , G03F9/00 , G06F17/50 , H01L21/027
CPC分类号： G03F1/36
摘要： A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.
摘要翻译：公开了一种相对于设计图案的微小步骤校正设计图案的设计图案校正方法，其包括提取从设计图案的顶点延伸的两个边缘中的至少一个，测量提取的边缘的长度，确定测量的边缘的长度是否短于预定值，如果确定提取的边缘的长度短于预定值，则提取连接到所提取的边缘的两个顶点，并且重新设计匹配的设计模式两个提取的顶点的位置彼此相对。

3. 发明申请

US20090077530A1 DESIGN PATTERN CORRECTING METHOD, DESIGN PATTERN FORMING METHOD, PROCESS PROXIMITY EFFECT CORRECTING METHOD, SEMICONDUCTOR DEVICE AND DESIGN PATTERN CORRECTING PROGRAM 失效
公开(公告)号：US20090077530A1
公开(公告)日：2009-03-19
申请号：US12269705
申请日：2008-11-12
申请人： TOSHIYA KOTANI , Shigeki Nojima , Shimon Maeda
发明人： TOSHIYA KOTANI , Shigeki Nojima , Shimon Maeda
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

4. 发明申请

US20090077529A1 DESIGN PATTERN CORRECTING METHOD, DESIGN PATTERN FORMING METHOD, PROCESS PROXIMITY EFFECT CORRECTING METHOD, SEMICONDUCTOR DEVICE AND DESIGN PATTERN CORRECTING PROGRAM 审中-公开
标题翻译：设计图案校正方法，设计图案形成方法，过程逼近效应校正方法，半导体器件和设计图案校正程序
公开(公告)号：US20090077529A1
公开(公告)日：2009-03-19
申请号：US12269687
申请日：2008-11-12
申请人： TOSHIYA KOTANI , Shigeki Nojima , Shimon Maeda
发明人： TOSHIYA KOTANI , Shigeki Nojima , Shimon Maeda
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.
摘要翻译：公开了一种相对于设计图案的微小步骤校正设计图案的设计图案校正方法，其包括提取从设计图案的顶点延伸的两个边缘中的至少一个，测量提取的边缘的长度，确定测量的边缘的长度是否短于预定值，如果确定提取的边缘的长度短于预定值，则提取连接到所提取的边缘的两个顶点，并且重新设计匹配的设计模式两个提取的顶点的位置彼此相对。

5. 发明授权

US07949967B2 Design Pattern correcting method, process proximity effect correcting method, and semiconductor device manufacturing method 失效
标题翻译：设计图案校正方法，过程接近效应校正方法和半导体器件制造方法
公开(公告)号：US07949967B2
公开(公告)日：2011-05-24
申请号：US12269705
申请日：2008-11-12
申请人： Toshiya Kotani , Shigeki Nojima , Shimon Maeda
发明人： Toshiya Kotani , Shigeki Nojima , Shimon Maeda
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.
摘要翻译：公开了一种相对于设计图案的微小步骤校正设计图案的设计图案校正方法，其包括提取从设计图案的顶点延伸的两个边缘中的至少一个，测量提取的边缘的长度，确定测量的边缘的长度是否短于预定值，如果确定提取的边缘的长度短于预定值，则提取连接到所提取的边缘的两个顶点，并且重新设计匹配的设计模式两个提取的顶点的位置彼此。

6. 发明申请

US20090037852A1 PATTERN DATA GENERATION METHOD AND PATTERN DATA GENERATION PROGRAM 有权
标题翻译：模式数据生成方法和模式数据生成程序
公开(公告)号：US20090037852A1
公开(公告)日：2009-02-05
申请号：US12180244
申请日：2008-07-25
申请人： Sachiko KOBAYASHI , Suigen Kyoh , Shimon Maeda
发明人： Sachiko KOBAYASHI , Suigen Kyoh , Shimon Maeda
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A pattern data generation method of an aspect of the present invention, the method includes creating at least one modification guide to modify a modification target point contained in pattern data, evaluating the modification guides on the basis of an evaluation item, the evaluation item being a change in the shape of the pattern data for the modification target point caused by the modification based on the modification guides or a change in electric characteristics of a pattern formed in accordance with the pattern data, selecting a predetermined modification guide from among the modification guides on the basis of the evaluation result of the modification guides, and modifying the modification target point in accordance with the selected modification guide.
摘要翻译：本发明的一个方式的图形数据生成方法，该方法包括创建至少一个修改指南，以修改包含在图案数据中的修改目标点，基于评估项目评估修改指南，评估项目是基于修改引导引起的修改目标点的图案数据的形状的改变或根据图案数据形成的图案的电特性的变化，从修改引导件中选择预定的修改指南修改指南的评估结果的基础，以及根据所选择的修改指南修改修改目标点。

7. 发明授权

US07917871B2 Method and program for pattern data generation using a modification guide 有权
标题翻译：使用修改指南生成图形数据的方法和程序
公开(公告)号：US07917871B2
公开(公告)日：2011-03-29
申请号：US12180244
申请日：2008-07-25
申请人： Sachiko Kobayashi , Suigen Kyoh , Shimon Maeda
发明人： Sachiko Kobayashi , Suigen Kyoh , Shimon Maeda
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A pattern data generation method of an aspect of the present invention, the method includes creating at least one modification guide to modify a modification target point contained in pattern data, evaluating the modification guides on the basis of an evaluation item, the evaluation item being a change in the shape of the pattern data for the modification target point caused by the modification based on the modification guides or a change in electric characteristics of a pattern formed in accordance with the pattern data, selecting a predetermined modification guide from among the modification guides on the basis of the evaluation result of the modification guides, and modifying the modification target point in accordance with the selected modification guide.
摘要翻译：本发明的一个方式的图形数据生成方法，该方法包括创建至少一个修改指南，以修改包含在图案数据中的修改目标点，基于评估项目评估修改指南，评估项目是基于修改引导引起的修改目标点的图案数据的形状的改变或根据图案数据形成的图案的电特性的变化，从修改引导件中选择预定的修改指南修改指南的评估结果的基础，以及根据所选择的修改指南修改修改目标点。

8. 发明授权

US08234596B2 Pattern data creating method, pattern data creating program, and semiconductor device manufacturing method 有权
标题翻译：图案数据创建方法，图案数据创建程序和半导体器件制造方法
公开(公告)号：US08234596B2
公开(公告)日：2012-07-31
申请号：US12552010
申请日：2009-09-01
申请人： Ryuji Ogawa , Masahiro Miyairi , Shimon Maeda , Suigen Kyoh , Satoshi Tanaka
发明人： Ryuji Ogawa , Masahiro Miyairi , Shimon Maeda , Suigen Kyoh , Satoshi Tanaka
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A pattern data creating method according to an embodiment of the present invention comprises: extracting marginal error patterns using a first result obtained by applying process simulation to mask pattern data based on an evaluation target cell pattern, applying the process simulation to mask pattern data based on an evaluation target cell pattern with peripheral environment pattern created by arranging a peripheral environment pattern in the marginal error patterns such that a second result obtained by creating mask pattern data and applying the process simulation to the mask pattern data is more deteriorated than the first result, and correcting the evaluation target cell pattern or the mask pattern data based on the evaluation target cell pattern when there is a fatal error.
摘要翻译：根据本发明的实施例的图形数据创建方法包括：使用通过应用过程模拟获得的第一结果来提取边缘误差模式以基于评估目标单元图案来屏蔽图案数据，将过程模拟应用于基于通过将周边环境图案布置在边缘误差图案中，使得通过创建掩模图案数据获得的第二结果和对掩模图案数据应用处理模拟而得到的第一结果比第一结果更差，从而产生具有周边环境图案的评估对象单元图案，以及当存在致命错误时，基于评估对象单元图案来校正评估对象单元格图案或掩模图案数据。

9. 发明申请

US20100081294A1 PATTERN DATA CREATING METHOD, PATTERN DATA CREATING PROGRAM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
标题翻译：图形数据创建方法，图形数据创建程序和半导体器件制造方法
公开(公告)号：US20100081294A1
公开(公告)日：2010-04-01
申请号：US12552010
申请日：2009-09-01
申请人： Ryuji OGAWA , Masahiro Miyairi , Shimon Maeda , Suigen Kyoh , Satoshi Tanaka
发明人： Ryuji OGAWA , Masahiro Miyairi , Shimon Maeda , Suigen Kyoh , Satoshi Tanaka
IPC分类号： H01L21/027 , G06F17/50
CPC分类号： G03F1/36
摘要： A pattern data creating method according to an embodiment of the present invention comprises: extracting marginal error patterns using a first result obtained by applying process simulation to mask pattern data based on an evaluation target cell pattern, applying the process simulation to mask pattern data based on an evaluation target cell pattern with peripheral environment pattern created by arranging a peripheral environment pattern in the marginal error patterns such that a second result obtained by creating mask pattern data and applying the process simulation to the mask pattern data is more deteriorated than the first result, and correcting the evaluation target cell pattern or the mask pattern data based on the evaluation target cell pattern when there is a fatal error.
摘要翻译：根据本发明的实施例的图形数据创建方法包括：使用通过应用过程模拟获得的第一结果来提取边缘误差模式以基于评估目标单元图案来屏蔽图案数据，将过程模拟应用于基于通过将周边环境图案布置在边缘误差图案中，使得通过创建掩模图案数据获得的第二结果和对掩模图案数据应用处理模拟而得到的第一结果比第一结果更差，从而产生具有周边环境图案的评估对象单元图案，以及当存在致命错误时，基于评估对象单元图案来校正评估对象单元格图案或掩模图案数据。

10. 发明申请

US20100067777A1 EVALUATION PATTERN GENERATING METHOD, COMPUTER PROGRAM PRODUCT, AND PATTERN VERIFYING METHOD 审中-公开
标题翻译：评估模式生成方法，计算机程序产品和模式验证方法
公开(公告)号：US20100067777A1
公开(公告)日：2010-03-18
申请号：US12536900
申请日：2009-08-06
申请人： Katsuyoshi Kodera , Satoshi Tanaka , Shimon Maeda , Suigen Kyoh , Soichi Inoue , Ryuji Ogawa
发明人： Katsuyoshi Kodera , Satoshi Tanaka , Shimon Maeda , Suigen Kyoh , Soichi Inoue , Ryuji Ogawa
IPC分类号： G06K9/00
CPC分类号： G03F1/44 , G03F1/36
摘要： An evaluation pattern generating method including dividing a peripheral area of an evaluation target pattern into a plurality of meshes; calculating an image intensity of a circuit pattern when the evaluation target pattern is transferred onto a wafer by a lithography process in a case where a mask function value is given to a predetermined mesh; calculating a mask function value of the mesh so that a cost function of the image intensity, in which an optical image characteristic amount that affects a transfer performance of the evaluation target pattern to the wafer is set to the image intensity, satisfies a predetermined reference when evaluating a lithography performance of the evaluation target pattern; and generating an evaluation pattern corresponding to the mask function value.
摘要翻译： 1.一种评价图案生成方法，包括将评价对象图案的周边区域划分为多个网格; 当将掩模函数值赋予预定网格时，通过光刻处理将评估对象图案转印到晶片上时，计算电路图案的图像强度; 计算网格的掩码函数值，使得影响评估对象图案对晶片的转印性能的光学图像特征量被设置为图像强度的图像强度的成本函数满足预定参考，当评估目标模式的光刻性能评估; 以及生成与所述掩模功能值对应的评估图案。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式