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1. 发明专利

AT450001T 未知
公开(公告)号：AT450001T
公开(公告)日：2009-12-15
申请号：AT05747426
申请日：2005-05-11
申请人： SUN MICROSYSTEMS INC
发明人： CHAUDHRY SHAILENDER , TREMBLAY MARC , CAPRIOLI PAUL
IPC分类号： G06F9/38
摘要： One embodiment of the present invention provides a processor which selectively fetches cache lines for store instructions during speculative-execution. During normal execution, the processor issues instructions for execution in program order. Upon encountering an instruction which generates a launch condition, the processor performs a checkpoint and begins the execution of instructions in a speculative-execution mode. Upon encountering a store instruction during the speculative-execution mode, the processor checks an L1 data cache for a matching cache line and checks a store buffer for a store to a matching cache line. If a matching cache line is already present in the L1 data cache or if the store to a matching cache line is already present in the store buffer, the processor suppresses generation of the fetch for the cache line. Otherwise, the processor generates a fetch for the cache line.

2. 发明专利

AU2003303438A8 Performing hardware scout threading in a system that supports simultaneous multithreading 未知
公开(公告)号：AU2003303438A8
公开(公告)日：2004-07-22
申请号：AU2003303438
申请日：2003-12-19
申请人： SUN MICROSYSTEMS INC
发明人： TREMBLAY MARC , CHAUDHRY SHAILENDER
IPC分类号： G06F9/00 , G06F9/30 , G06F9/38 , G06F12/08

3. 发明专利

AU2003303438A1 PERFORMING HARDWARE SCOUT THREADING IN A SYSTEM THAT SUPPORTS SIMULTANEOUS MULTITHREADING 未知
公开(公告)号：AU2003303438A1
公开(公告)日：2004-07-22
申请号：AU2003303438
申请日：2003-12-19
申请人： SUN MICROSYSTEMS INC
发明人： CHAUDHRY SHAILENDER , TREMBLAY MARC
IPC分类号： G06F9/00 , G06F9/30 , G06F9/38 , G06F12/08 , G06F9/40

4. 发明专利

AU2002250576A1 Reverse directory for facilitating accesses involving a lower-level cache 未知
公开(公告)号：AU2002250576A1
公开(公告)日：2002-10-28
申请号：AU2002250576
申请日：2002-04-11
申请人： SUN MICROSYSTEMS INC
发明人： CHAUDHRY SHAILENDER , TREMBLAY MARC
IPC分类号： G06F12/08
摘要： One embodiment of the present invention provides a multiprocessor system that includes a number of processors with higher-level caches that perform memory accesses through a lower-level cache. This multiprocessor system also includes a reverse directory coupled to the lower-level cache, which includes entries corresponding to lines in the higher-level caches, wherein each entry identifies an associated entry in the lower-level cache. In one embodiment of the present invention, the higher-level cache is a set-associative cache, and storing the information within the reverse directory specifies a way location in the higher-level cache in which the line is to be stored. The system is configured to use this way information during a subsequent invalidation operation to invalidate the line in the higher-level cache without having to perform a lookup in the higher-level cache to determine the way location of the line in the higher-level cache.

5. 发明专利

DE60317878D1 未知
公开(公告)号：DE60317878D1
公开(公告)日：2008-01-17
申请号：DE60317878
申请日：2003-02-21
申请人： SUN MICROSYSTEMS INC
发明人： TREMBLAY MARC , CHAUDHRY SHAILENDER
IPC分类号： G06F9/38 , G06F9/35 , G06F9/46 , G06F12/08
摘要： Techniques have been developed whereby likely pointer values are identified at runtime and contents of corresponding storage location can be prefetched into a cache hierarchy to reduce effective memory access latencies. In some realizations, one or more writable stores are defined in a processor architecture to delimit a portion or portions of a memory address space.

6. 发明专利

AU2003222650A1 METHOD AND APPARATUS FOR PROVIDING ERROR CORRECTION WITHIN A REGISTER FILE OF A CPU 未知
公开(公告)号：AU2003222650A1
公开(公告)日：2003-12-02
申请号：AU2003222650
申请日：2003-04-17
申请人： SUN MICROSYSTEMS INC
发明人： TREMBLAY MARC , CHAUDHRY SHAILENDER , JACOBSON QUINN
IPC分类号： G06F11/07 , G06F11/10 , G06F11/14 , H03M13/00
摘要： A system that facilitates error correction within a register file in a central processing unit (CPU). During execution of an instruction by the CPU, the system retrieves a dataword and an associated syndrome from a source register in the register file. Next, the system uses information in the dataword and the associated syndrome to detect, and if necessary correct, an error in the dataword or associated syndrome. This error detection and correction takes place in parallel with using the dataword to perform a computational operation specified by the instruction. If an error is detected, the system prevents the instruction from performing a writeback to a destination register in the register file. The system also writes a corrected dataword to the source register in the register file. Next, the system flushes the instruction pipeline, and restarts execution of the instruction so that the corrected dataword is retrieved for the computational operation.

7. 发明专利

AU2002330027A1 Method and apparatus for decoupling tag and data accesses in a cache memory 未知
公开(公告)号：AU2002330027A1
公开(公告)日：2003-04-01
申请号：AU2002330027
申请日：2002-09-13
申请人： SUN MICROSYSTEMS INC
发明人： TREMBLAY MARC , CHAUDHRY SHAILENDER
IPC分类号： G06F12/08 , G06F9/38
摘要： One embodiment of the present invention provides a system that decouples a tag access from a corresponding data access within a cache memory. The system operates by receiving a memory request at the cache memory, wherein the memory request includes an address identifying a memory location. Next, the system performs the tag access by looking up at least one tag from a tag array within the cache memory and comparing the at least one tag with a tag portion of the address to determine if a cache line containing the address is located in the cache memory. If the cache line containing the address is located in the cache memory but a data array containing the cache line is busy, the system performs the corresponding data access at a later time when the data array becomes free. Furthermore, if the memory request is for a load operation, the corresponding data access takes place without waiting for preceding load operations to complete.

8. 发明专利

AU2002258823A1 Method and apparatus for updating an error-correcting code during a partial line store 未知
公开(公告)号：AU2002258823A1
公开(公告)日：2002-11-05
申请号：AU2002258823
申请日：2002-04-17
申请人： SUN MICROSYSTEMS INC
发明人： CHAUDHRY SHAILENDER , TREMBLAY MARC
IPC分类号： G06F11/08 , G06F11/10 , G11C11/413 , G11C11/419 , G11C29/00
摘要： One embodiment of the present invention provides a system that updates an error-correcting code for a line when only a portion of the line is updated during a store operation. The system operates by receiving the store operation, wherein the store operation includes new data to be stored to the portion of the line, as well as an address of the portion of the line. Next, the system reads old data for the portion of the line from the address, and then stores the new data to the portion of the line at the address. The system also updates the existing error-correcting code for the line to reflect the new data. This involves calculating a new error-correcting code for the line from the existing error-correcting code, the old data and the new data. The system then replaces the existing error-correcting code with the new error-correcting code.

9. 发明专利

AU2002252647A1 Providing fault-tolerance by comparing addresses and data from redundant processors running in lock-step 未知
公开(公告)号：AU2002252647A1
公开(公告)日：2002-10-28
申请号：AU2002252647
申请日：2002-04-11
申请人： SUN MICROSYSTEMS INC
发明人： TREMBLAY MARC , CHAUDHRY SHAILENDER
IPC分类号： G06F12/08 , G06F11/00 , G06F11/16 , G06F11/18 , G06F11/22
摘要： One embodiment of the present invention provides a system that facilitates fault-tolerance by using redundant processors. This system operates by receiving store operations from a plurality of redundant processors running the same code in lockstep. The system compares the store operations to determine if the store operations are identical, thereby indicating that the redundant processors are operating correctly. If the store operations are identical, the system combines the store operations into a combined store operation, and forwards the combined store operation to a system memory that is shared between the redundant processors. If the store operations are not identical, the system indicates an error condition. In a variation on this embodiment, the system similarly combines store operations.

10. 发明专利

AU6972701A Marking memory elements based upon usage of accessed information during speculative execution 未知
公开(公告)号：AU6972701A
公开(公告)日：2001-12-11
申请号：AU6972701
申请日：2001-05-30
申请人： SUN MICROSYSTEMS INC
发明人： CHAUDHRY SHAILENDER , TREMBLAY MARC
IPC分类号： G06F9/38
摘要： One embodiment of the present invention provides a system that marks memory elements based upon how information retrieved from the memory elements affects speculative program execution. This system operates by allowing a programmer to examine source code that is to be compiled into executable code for a head thread that executes program instructions, and for a speculative thread that executes program instructions in advance of the head thread. During read operations to memory elements by the speculative thread, this executable code generally causes the speculative thread to update status information associated with the memory elements to indicate that the memory elements have been read by the speculative thread. Next, the system allows the programmer to identify a given read operation directed to a given memory element, wherein a given value retrieved from the given memory element during the given read operation does not affect subsequent execution of the speculative thread. The programmer is then allowed to insert a hint into the source code specifying that the speculative thread is not to update status information during the given read operation directed to the given memory element. Next, the system compiles the source code, including the hint, into the executable code, so that during the given read operation, the executable code does not cause the speculative thread to update status information associated with the given memory element to indicate that the given memory element has been read by the speculative thread.

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