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    • 1. 发明专利
      AT450001T  未知
    • AT450001T
    • 2009-12-15
    • AT05747426
    • 2005-05-11
    • SUN MICROSYSTEMS INC
    • CHAUDHRY SHAILENDER , TREMBLAY MARC , CAPRIOLI PAUL
    • G06F9/38
    • One embodiment of the present invention provides a processor which selectively fetches cache lines for store instructions during speculative-execution. During normal execution, the processor issues instructions for execution in program order. Upon encountering an instruction which generates a launch condition, the processor performs a checkpoint and begins the execution of instructions in a speculative-execution mode. Upon encountering a store instruction during the speculative-execution mode, the processor checks an L1 data cache for a matching cache line and checks a store buffer for a store to a matching cache line. If a matching cache line is already present in the L1 data cache or if the store to a matching cache line is already present in the store buffer, the processor suppresses generation of the fetch for the cache line. Otherwise, the processor generates a fetch for the cache line.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 6. 发明专利
      DE602005017909D1  未知
    • DE602005017909D1
    • 2010-01-07
    • DE602005017909
    • 2005-05-11
    • SUN MICROSYSTEMS INC
    • CHAUDHRY SHAILENDER , TREMBLAY MARC , CAPRIOLI PAUL
    • G06F9/38
    • One embodiment of the present invention provides a processor which selectively fetches cache lines for store instructions during speculative-execution. During normal execution, the processor issues instructions for execution in program order. Upon encountering an instruction which generates a launch condition, the processor performs a checkpoint and begins the execution of instructions in a speculative-execution mode. Upon encountering a store instruction during the speculative-execution mode, the processor checks an L1 data cache for a matching cache line and checks a store buffer for a store to a matching cache line. If a matching cache line is already present in the L1 data cache or if the store to a matching cache line is already present in the store buffer, the processor suppresses generation of the fetch for the cache line. Otherwise, the processor generates a fetch for the cache line.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 7. 发明专利
      GB2413865B Method and apparatus for avoiding WAW hazards in a processor 未知
    • Method and apparatus for avoiding WAW hazards in a processor
    • GB2413865B
    • 2007-05-30
    • GB0507372
    • 2005-04-12
    • SUN MICROSYSTEMS INC
    • CAPRIOLI PAUL , CHAUDHRY SHAILENDER
    • G06F9/38 , G06F15/00
    • One embodiment of the present invention provides a system that avoids write-after-write (WAW) hazards while speculatively executing instructions. The system starts in a normal execution mode, wherein the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint, defers the instruction, and executes subsequent instructions in an execute-ahead mode. During this execute-ahead mode, instructions that cannot be executed because of unresolved data dependencies are deferred, and other non-deferred instructions are executed in program order. If an unresolved data dependency is resolved during the execute-ahead mode, the system moves into a deferred mode wherein the system executes deferred instructions. While executing a deferred instruction, if dependency information for an associated destination register indicates that a WAW hazard potentially exists with a following non-deferred instruction, the system executes the deferred instruction to produce a result, and forwards the result to be used by subsequent instructions in a pipeline and/or deferred queue for the processor. The system does so without committing the result to the architectural state of the destination register. In this way, the system makes the result available to the subsequent instructions without overwriting a result produced by the following non-deferred instruction, thereby avoiding a WAW hazard.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 10. 发明专利
      GB2430289A Selective execution of deferred instructions 未知
    • Selective execution of deferred instructions
    • GB2430289A
    • 2007-03-21
    • GB0701004
    • 2005-05-11
    • SUN MICROSYSTEMS INC
    • CHAUDHRY SHAILENDER , CAPRIOLI PAUL , TREMBLAY MARC
    • G06F9/38
    • A system which selectively executes deferred instructions following a return of a long-latency operation in a processor that supports speculative-execution. When the processor encounters a long-latency operation, the processor records the long-latency operation in a long-latency scoreboard, wherein each entry in the long-latency scoreboard includes a deferred buffer start index. Upon encountering an unresolved data dependency, the processor performs a checkpointing operation and executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred into a deferred buffer, and wherein other non-deferred instructions are executed in program order. Upon encountering a deferred instruction that depends on a long-latency operation within the long-latency scoreboard, the processor updates a deferred buffer start index associated with the long-latency operation to point to position in the deferred buffer occupied by the deferred instruction. When a long-latency operation returns, the processor executes instructions in the deferred buffer starting at the deferred buffer start index for the returning long-latency operation.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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