专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2007123541A1 VIRTUALIZED PARTITIONABLE SHARED NETWORK INTERFACE 审中-公开
标题翻译：虚拟化可分割的共享网络接口
公开(公告)号：WO2007123541A1
公开(公告)日：2007-11-01
申请号：PCT/US2006/015549
申请日：2006-04-21
申请人： SUN MICROSYSTEMS, INC. , MULLER, Shimon , HENDEL, Ariel , GAJJAR, Yatin , WONG, Michael
发明人： MULLER, Shimon , HENDEL, Ariel , GAJJAR, Yatin , WONG, Michael
IPC分类号： G06F13/28 , G06F13/16
CPC分类号： G06F9/5077
摘要： A network system having a plurality of processing partitions which includes a network interface unit coupled to a plurality of processing entities is disclosed. The network interface unit includes a plurality of memory access channels. The plurality of memory access channels is virtualized. The network interface unit is shared among the plurality of processing partitions.
摘要翻译：公开了具有多个处理分区的网络系统，其中包括耦合到多个处理实体的网络接口单元。网络接口单元包括多个存储器访问通道。多个存储器访问通道被虚拟化。网络接口单元在多个处理分区之间共享。

2. 发明申请

WO2007123520A1 METHOD AND SYSTEM FOR SCALING BY PARALLELIZING NETWORK WORKLOAD 审中-公开
标题翻译：通过并行网络工作量进行分级的方法和系统
公开(公告)号：WO2007123520A1
公开(公告)日：2007-11-01
申请号：PCT/US2006/015078
申请日：2006-04-21
申请人： SUN MICROSYSTEMS, INC. , HENDEL, Ariel , WONG, Michael , GAJJAR, Yatin , MULLER, Shimon
发明人： HENDEL, Ariel , WONG, Michael , GAJJAR, Yatin , MULLER, Shimon
IPC分类号： H04L12/56
CPC分类号： G06F13/28
摘要： A method for scaling a network system which includes providing at least one network interface and providing a flexible association between packets and a plurality of processing entities via the plurality of memory access channels. Each network interface including a plurality of memory access channels.
摘要翻译：一种用于缩放网络系统的方法，其包括提供至少一个网络接口并且经由多个存储器访问信道提供分组与多个处理实体之间的灵活关联。每个网络接口包括多个存储器访问通道。

3. 发明申请

WO2007123532A1 ASYMMETRICAL PROCESSING FOR NETWORKING FUNCTIONS AND DATA PATH OFFLOAD 审中-公开
标题翻译：用于网络功能和数据路径不对称的非对称处理
公开(公告)号：WO2007123532A1
公开(公告)日：2007-11-01
申请号：PCT/US2006/015408
申请日：2006-04-21
申请人： SUN MICROSYSTEMS, INC. , MULLER, Shimon , HENDEL, Ariel , GAJJAR, Yatin , WONG, Michael , PURI, Rahoul , LIN, May
发明人： MULLER, Shimon , HENDEL, Ariel , GAJJAR, Yatin , WONG, Michael , PURI, Rahoul , LIN, May
IPC分类号： H04L12/56
CPC分类号： H04L47/10
摘要： A network system which includes a plurality of processing entities, an interconnect device coupled to the plurality of processing entities, a memory system coupled to the interconnect device and the plurality of processing entities, a network interface unit coupled to the plurality of processing entities and the memory system via the interconnect device. The network interface includes a memory access module and a packet classifier. The memory access module includes a plurality of parallel memory access channels. The packet classifier provides a flexible association between packets and the plurality of processing entities via the plurality of memory access channels.
摘要翻译：一种网络系统，其包括多个处理实体，耦合到所述多个处理实体的互连设备，耦合到所述互连设备和所述多个处理实体的存储器系统，耦合到所述多个处理实体的网络接口单元和内存系统通过互连设备。网络接口包括存储器访问模块和分组分类器。存储器访问模块包括多个并行存储器存取通道。分组分类器通过多个存储器访问信道提供分组与多个处理实体之间的灵活关联。

4. 发明申请

WO2007123517A1 ASYMMETRICAL PROCESSING FOR NETWORKING FUNCTIONS AND DATA PATH OFFLOAD 审中-公开
标题翻译：用于网络功能和数据路径不对称的非对称处理
公开(公告)号：WO2007123517A1
公开(公告)日：2007-11-01
申请号：PCT/US2006/014974
申请日：2006-04-21
申请人： SUN MICROSYSTEMS, INC. , HENDEL, Ariel , GAJJAR, Yatin , LIN, May , PURI, Rahoul , WONG, Michael
发明人： HENDEL, Ariel , GAJJAR, Yatin , LIN, May , PURI, Rahoul , WONG, Michael
IPC分类号： G06F13/28
CPC分类号： H04L67/1002 , H04L67/1023 , H04L69/02
摘要： A network system which provides asymmetrical processing for networking functions and data path offload. A network interface unit is operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. In various embodiments of the invention, predetermined subsets of the plurality of processing entities are operably associated with predetermined subsets of the plurality of memory units thereby defining a plurality of asymmetrical data processing partitions. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing partitions. In various embodiments of the invention, the asymmetrical data processing partitions can comprise a plurality of processor cores, a single processor core, a combination of strands of an individual processor core or a single strand of an individual processor core. The asymmetrical data processing partitions are scalable by adding additional processing entities.
摘要翻译：一种为网络功能和数据路径卸载提供不对称处理的网络系统。网络接口单元可操作地连接到多个处理实体和定义共享存储器空间的多个存储器单元。网络接口单元还包括存储器访问模块，其包括多个存储器访问通道，分组分类器和可操作以控制由网络传送的数据的处理的多个调度控制模块。在本发明的各种实施例中，多个处理实体中的预定子集可操作地与多个存储器单元中的预定子集相关联，从而定义多个非对称数据处理分区。分组分类器可操作以提供分组与多个非对称数据处理分区之间的关联。在本发明的各种实施例中，非对称数据处理分区可以包括多个处理器核心，单个处理器核心，单个处理器核心的线束组合或单个处理器核心的单个链路的组合。不对称数据处理分区可通过添加附加处理实体进行扩展。

5. 发明申请

WO2004062207A1 METHOD AND APPARATUS FOR STARVATION-FREE SCHEDULING OF COMMUNICATIONS 审中-公开
标题翻译：无通信调度的方法和装置
公开(公告)号：WO2004062207A1
公开(公告)日：2004-07-22
申请号：PCT/US2003/033381
申请日：2003-10-21
申请人： SUN MICROSYSTEMS, INC.
发明人： HENDEL, Ariel , CHAO, Fu-Kuang, Frank
IPC分类号： H04L12/56
CPC分类号： H04L47/24 , H04L47/39 , H04L47/50 , H04L47/56 , H04L47/6235 , H04L47/6285
摘要： A system and method for scheduling communications from a communication interface. Each of multiple send queues is associated with a destination and assigned to a logical communication channel. A list of stalled queues identifies those send queues for which a constraint restricts scheduling. When a queue is to be selected for service, a scheduler first attempts to find a member of the stalled queues list that is no longer stalled (e.g., any constraints were satisfied). Such a queue is selected for service if it exists. If there is no such queue, then all logical channels are examined and, from a list of send queues assigned to a selected logical channel, a send queue is selected for servicing. After a queue is scheduled from the stalled queues list, the list of queues assigned to its logical channel is adjusted (e.g., to place the queue at the tail of the list).
摘要翻译：一种用于从通信接口调度通信的系统和方法。多个发送队列中的每一个都与目的地相关联并分配给逻辑通信信道。停滞队列的列表标识约束限制调度的发送队列。当队列被选择用于服务时，调度器首先尝试找到不再停滞的停滞队列列表的成员（例如，满足任何约束）。如果存在这样的队列被选择用于服务。如果没有这样的队列，则检查所有逻辑信道，并且从分配给所选逻辑信道的发送队列的列表中选择发送队列进行维修。在从停滞的队列列表调度队列之后，调整分配给其逻辑信道的队列的列表（例如，将队列放置在列表的尾部）。

6. 发明申请

WO2004010311A2 METHOD AND APPARATUS FOR ZERO-COPY RECEIVE BUFFER MANAGEMENT 审中-公开
标题翻译：用于零拷贝接收缓冲器管理的方法和设备
公开(公告)号：WO2004010311A2
公开(公告)日：2004-01-29
申请号：PCT/US2003/018928
申请日：2003-06-17
申请人： SUN MICROSYSTEMS, INC.
发明人： HENDEL, Ariel , BEHRENS, Jochen , SIDDABATHUNI, Ajoy
IPC分类号： G06F13/00
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9052 , H04L49/9094
摘要： An apparatus and method for managing the receipt of communication traffic in the form of packets or other units. The apparatus includes a communication interface (e.g., a NIC, a TCA) coupled to one or more host computer systems. Through Direct Memory Access (DMA) operations, the interface reassembles payloads of received packets in host buffers based on their sequence numbers, without buffering them in the interface. Packet headers are separated from the payloads and passed to a host for protocol processing after the payload DMA is completed. Host buffers may be of virtually any size. For each communication connection, state information is maintained on the interface, which may identify an upper level protocol so that an upper level protocol header is passed to the host as part of the packet header, not as part of the payload. Protocol termination remains in the host.
摘要翻译：用于管理以分组或其他单元的形式接收通信业务的设备和方法。该设备包括耦合到一个或多个主计算机系统的通信接口（例如，NIC，TCA）。通过直接内存访问（Direct Memory Access，DMA）操作，接口基于序列号重新组装主机缓冲区中接收数据包的有效负载，而不会在接口中缓冲它们。数据包头与有效负载分离，并在有效负载DMA完成后传递给主机进行协议处理。主机缓冲区实际上可以是任何大小的。对于每个通信连接，状态信息都保存在接口上，这可以识别上层协议，以便上层协议报头作为数据包报头的一部分传递到主机，而不是作为有效负载的一部分。协议终止保留在主机中。

7. 发明申请

WO2003017620A1 PROTOCOL PROCESSOR 审中-公开
标题翻译：协议处理器
公开(公告)号：WO2003017620A1
公开(公告)日：2003-02-27
申请号：PCT/US2002/024050
申请日：2002-07-23
申请人： SUN MICROSYSTEMS, INC.
发明人： POGGIO, Andrew , HEJZA, Leo , HENDEL, Ariel
IPC分类号： H04L29/06
CPC分类号： H04L49/9026 , H04L47/62 , H04L49/90 , H04L49/9057 , H04L49/9073 , H04L69/22 , H04L69/28
摘要： A protocol processor is a specialized processor dedicated to extracting data (i.e., a payload) from an incoming communication (e.g., packet) and configuring outgoing data for transmission, and includes one or more protocol processing elements (PPE). Each PPE may be programmed to handle any set of communication protocols, and includes a set of large registers (e.g., 128 bytes, 256 bytes). A PPE also includes a parse unit for parsing packets to retrieve certain information and a lookup unit for accessing a control block indicating how to process an incoming packet or outgoing payload. A modification unit removes headers from incoming packets and/or adds them to outgoing data. A timer unit manages a large number of timers (e.g., for different communication streams). A control block cache may store recently accessed control blocks, and a data streaming unit streams packets (or packet portions) into and out of the registers.
摘要翻译：协议处理器是专用于从输入通信（例如，分组）提取数据（即，有效载荷）并配置用于传输的输出数据的专用处理器，并且包括一个或多个协议处理元件（PPE）。每个PPE可以被编程为处理任何一组通信协议，并且包括一组大寄存器（例如，128字节，256字节）。 PPE还包括用于解析分组以检索某些信息的解析单元和用于访问指示如何处理输入分组或传出有效载荷的控制块的查找单元。修改单元从输入数据包中删除头文件和/或将其添加到传出数据。定时器单元管理大量的定时器（例如，用于不同的通信流）。控制块高速缓存可以存储最近访问的控制块，并且数据流单元将分组（或分组部分）流入和移出寄存器。

8. 发明授权

EP0937353B1 ROUTING IN A MULTI-LAYER DISTRIBUTED NETWORK ELEMENT 失效
标题翻译：路由在分布式多层网络ELEMENT
公开(公告)号：EP0937353B1
公开(公告)日：2009-07-29
申请号：EP98932859.6
申请日：1998-06-24
申请人： SUN MICROSYSTEMS, INC.
发明人： HENDEL, Ariel , MULLER, Shimon , ZAUMEN, William, T. , YEUNG, Louise
IPC分类号： H04L12/28 , H04L12/56 , H04Q5/22 , H04L12/18
CPC分类号： H04L12/18 , H04L12/4645 , H04L45/00 , H04L45/60 , H04L49/602
摘要： A multi-layer distributed network element (201) for relaying packets according to known routing protocols. A distributed architecture of multiple subsystems (201) delivers routing at wire-speed performance across subnetworks. Each subsystem (210) includes a forwarding memory (213) and an associated memory (214) and is configured to identify unicast and multicast packets for routing purposes, modify the packets in hardware, including replace VLAN information, and forward the packets to the next hop. The routing decisions are made in the inbound subsystem, and packets are forwarded, if necessary given the network topology, through a separate outbound subsystem.

9. 发明公开

EP2016718A1 METHOD AND SYSTEM FOR SCALING BY PARALLELIZING NETWORK WORKLOAD 有权转让
标题翻译：方法和系统分割由并行化网络的工作量
公开(公告)号：EP2016718A1
公开(公告)日：2009-01-21
申请号：EP06750961.2
申请日：2006-04-21
申请人： SUN MICROSYSTEMS, INC.
发明人： HENDEL, Ariel , WONG, Michael , GAJJAR, Yatin , MULLER, Shimon
IPC分类号： H04L12/56
CPC分类号： G06F13/28
摘要： A method for scaling a network system which includes providing at least one network interface and providing a flexible association between packets and a plurality of processing entities via the plurality of memory access channels. Each network interface including a plurality of memory access channels.

10. 发明公开

EP0992056A2 SEARCH ENGINE ARCHITECTURE FOR A HIGH PERFORMANCE MULTI-LAYER SWITCH ELEMENT 有权转让
标题翻译：搜索引擎架构FOR多层高性能开关元
公开(公告)号：EP0992056A2
公开(公告)日：2000-04-12
申请号：EP98932909.9
申请日：1998-06-25
申请人： SUN MICROSYSTEMS, INC.
发明人： MULLER, Shimon , HENDEL, Ariel , YEUNG, Louise
IPC分类号： H01J13/00
CPC分类号： H04L49/602 , H04L29/06 , H04L45/7453 , H04L49/201 , H04L49/205 , H04L49/3009 , H04L49/351 , H04L69/22
摘要： A multi-layer switch search engine architecture is provided. A switch fabric includes a search engine, and a packet header processing unit. The search engine (370) may be coupled to a forwarding database memory and one or more input ports. The search engine is configured to schedule and perform accesses to the forwarding database memory and to transfer forwarding decisions to the input ports. The header processing unit (360) is coupled to the search engine and includes an arbitrated interface (501-504) for coupling to the input ports. The header processing unit is configured to construct a search key for accessing the forwarding database memory based upon a predetermined portion of the packet header. The predetermined portion of the packet header is selected based upon a packet class with which the packet header is associated.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式