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1. 发明申请

WO2007123532A1 ASYMMETRICAL PROCESSING FOR NETWORKING FUNCTIONS AND DATA PATH OFFLOAD 审中-公开
标题翻译：用于网络功能和数据路径不对称的非对称处理
公开(公告)号：WO2007123532A1
公开(公告)日：2007-11-01
申请号：PCT/US2006/015408
申请日：2006-04-21
申请人： SUN MICROSYSTEMS, INC. , MULLER, Shimon , HENDEL, Ariel , GAJJAR, Yatin , WONG, Michael , PURI, Rahoul , LIN, May
发明人： MULLER, Shimon , HENDEL, Ariel , GAJJAR, Yatin , WONG, Michael , PURI, Rahoul , LIN, May
IPC分类号： H04L12/56
CPC分类号： H04L47/10
摘要： A network system which includes a plurality of processing entities, an interconnect device coupled to the plurality of processing entities, a memory system coupled to the interconnect device and the plurality of processing entities, a network interface unit coupled to the plurality of processing entities and the memory system via the interconnect device. The network interface includes a memory access module and a packet classifier. The memory access module includes a plurality of parallel memory access channels. The packet classifier provides a flexible association between packets and the plurality of processing entities via the plurality of memory access channels.
摘要翻译：一种网络系统，其包括多个处理实体，耦合到所述多个处理实体的互连设备，耦合到所述互连设备和所述多个处理实体的存储器系统，耦合到所述多个处理实体的网络接口单元和内存系统通过互连设备。网络接口包括存储器访问模块和分组分类器。存储器访问模块包括多个并行存储器存取通道。分组分类器通过多个存储器访问信道提供分组与多个处理实体之间的灵活关联。

2. 发明申请

WO2007123517A1 ASYMMETRICAL PROCESSING FOR NETWORKING FUNCTIONS AND DATA PATH OFFLOAD 审中-公开
标题翻译：用于网络功能和数据路径不对称的非对称处理
公开(公告)号：WO2007123517A1
公开(公告)日：2007-11-01
申请号：PCT/US2006/014974
申请日：2006-04-21
申请人： SUN MICROSYSTEMS, INC. , HENDEL, Ariel , GAJJAR, Yatin , LIN, May , PURI, Rahoul , WONG, Michael
发明人： HENDEL, Ariel , GAJJAR, Yatin , LIN, May , PURI, Rahoul , WONG, Michael
IPC分类号： G06F13/28
CPC分类号： H04L67/1002 , H04L67/1023 , H04L69/02
摘要： A network system which provides asymmetrical processing for networking functions and data path offload. A network interface unit is operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. In various embodiments of the invention, predetermined subsets of the plurality of processing entities are operably associated with predetermined subsets of the plurality of memory units thereby defining a plurality of asymmetrical data processing partitions. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing partitions. In various embodiments of the invention, the asymmetrical data processing partitions can comprise a plurality of processor cores, a single processor core, a combination of strands of an individual processor core or a single strand of an individual processor core. The asymmetrical data processing partitions are scalable by adding additional processing entities.
摘要翻译：一种为网络功能和数据路径卸载提供不对称处理的网络系统。网络接口单元可操作地连接到多个处理实体和定义共享存储器空间的多个存储器单元。网络接口单元还包括存储器访问模块，其包括多个存储器访问通道，分组分类器和可操作以控制由网络传送的数据的处理的多个调度控制模块。在本发明的各种实施例中，多个处理实体中的预定子集可操作地与多个存储器单元中的预定子集相关联，从而定义多个非对称数据处理分区。分组分类器可操作以提供分组与多个非对称数据处理分区之间的关联。在本发明的各种实施例中，非对称数据处理分区可以包括多个处理器核心，单个处理器核心，单个处理器核心的线束组合或单个处理器核心的单个链路的组合。不对称数据处理分区可通过添加附加处理实体进行扩展。

3. 发明公开

EP2016498A1 ASYMMETRICAL PROCESSING FOR NETWORKING FUNCTIONS AND DATA PATH OFFLOAD 有权转让
标题翻译：非对称处理联网功能和数据路径卸载
公开(公告)号：EP2016498A1
公开(公告)日：2009-01-21
申请号：EP06750889.5
申请日：2006-04-21
申请人： SUN MICROSYSTEMS, INC.
发明人： HENDEL, Ariel , GAJJAR, Yatin , LIN, May , PURI, Rahoul , WONG, Michael
IPC分类号： G06F13/28
CPC分类号： H04L67/1002 , H04L67/1023 , H04L69/02
摘要： A network system which provides asymmetrical processing for networking functions and data path offload. A network interface unit is operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. In various embodiments of the invention, predetermined subsets of the plurality of processing entities are operably associated with predetermined subsets of the plurality of memory units thereby defining a plurality of asymmetrical data processing partitions. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing partitions. In various embodiments of the invention, the asymmetrical data processing partitions can comprise a plurality of processor cores, a single processor core, a combination of strands of an individual processor core or a single strand of an individual processor core. The asymmetrical data processing partitions are scalable by adding additional processing entities.

4. 发明公开

EP2014028A1 ASYMMETRICAL PROCESSING FOR NETWORKING FUNCTIONS AND DATA PATH OFFLOAD 有权转让
标题翻译：网络功能和数据路径卸载的非对称处理
公开(公告)号：EP2014028A1
公开(公告)日：2009-01-14
申请号：EP06758535.6
申请日：2006-04-21
申请人： SUN MICROSYSTEMS, INC.
发明人： MULLER, Shimon , HENDEL, Ariel , GAJJAR, Yatin , WONG, Michael , PURI, Rahoul , LIN, May
IPC分类号： H04L12/56
CPC分类号： H04L47/10
摘要： A network system which includes a plurality of processing entities, an interconnect device coupled to the plurality of processing entities, a memory system coupled to the interconnect device and the plurality of processing entities, a network interface unit coupled to the plurality of processing entities and the memory system via the interconnect device. The network interface includes a memory access module and a packet classifier. The memory access module includes a plurality of parallel memory access channels. The packet classifier provides a flexible association between packets and the plurality of processing entities via the plurality of memory access channels.
摘要翻译：一种网络系统，包括多个处理实体，耦合到所述多个处理实体的互连设备，耦合到所述互连设备和所述多个处理实体的存储器系统，耦合到所述多个处理实体的网络接口单元和内存系统通过互连设备。网络接口包括存储器访问模块和分组分类器。存储器访问模块包括多个并行存储器访问通道。分组分类器经由多个存储器访问信道提供分组与多个处理实体之间的灵活关联。

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