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1. 发明申请

WO2010119792A1 SUBSTRATE, SUBSTRATE PROVIDED WITH THIN FILM, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：衬底，具有薄膜的衬底，半导体器件和制造半导体器件的方法
公开(公告)号：WO2010119792A1
公开(公告)日：2010-10-21
申请号：PCT/JP2010056206
申请日：2010-04-06
申请人： SUMITOMO ELECTRIC INDUSTRIES , HARADA SHIN , SASAKI MAKOTO , MASUDA TAKEYOSHI
发明人： HARADA SHIN , SASAKI MAKOTO , MASUDA TAKEYOSHI
IPC分类号： C30B29/36 , C23C16/32 , C23C16/42 , C30B25/20 , H01L21/02 , H01L21/205 , H01L21/329 , H01L21/336 , H01L21/337 , H01L21/338 , H01L29/12 , H01L29/47 , H01L29/78 , H01L29/80 , H01L29/808 , H01L29/812 , H01L29/861 , H01L29/872
CPC分类号： H01L29/808 , B24B7/17 , B24B7/228 , B24B37/08 , B24B37/10 , C30B25/20 , C30B29/36 , H01L21/02378 , H01L21/0243 , H01L21/02529 , H01L21/0465 , H01L29/02 , H01L29/045 , H01L29/063 , H01L29/0657 , H01L29/1608 , H01L29/66068 , H01L29/78 , H01L29/7802 , H01L29/7813 , H01L29/8083 , H01L29/812 , H01L29/8122 , H01L29/8128 , H01L29/8611 , H01L29/872
摘要： Provided are a substrate which suppresses deterioration of processing accuracy of a semiconductor device due to the warping of the substrate, a substrate provided with a thin film, a semiconductor device formed using the abovementioned substrate, and a method for manufacturing said semiconductor device. In the substrate (1), the diameter of the main surface (1a) is 2 inches or more, the bow value of the main surface (1a) is -40 µm to -5 µm, and the warp value of the main surface (1a) is 5 µm to 40 µm. The value of the surface roughness (Ra) of the main surface (1a) of the substrate (1) is preferably 1 nm or less and the value of the surface roughness (Ra) of the main surface (1b) is preferably 100 nm or less.
摘要翻译：提供了抑制由于基板的翘曲，设置有薄膜的基板，使用上述基板形成的半导体装置引起的半导体装置的加工精度劣化的基板及其制造方法。在基板（1）中，主表面（1a）的直径为2英寸以上，主面（1a）的弓形值为-40〜-5μm，主表面的翘曲值 1a）为5μm〜40μm。基板（1）的主表面（1a）的表面粗糙度（Ra）的值优选为1nm以下，主面（1b）的表面粗糙度（Ra）的值优选为100nm，减。

2. 发明申请

WO2012017796A1 SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCTION THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2012017796A1
公开(公告)日：2012-02-09
申请号：PCT/JP2011066063
申请日：2011-07-14
申请人： SUMITOMO ELECTRIC INDUSTRIES , MASUDA TAKEYOSHI , HARADA SHIN , HONAGA MISAKO , WADA KEIJI , HIYOSHI TORU
发明人： MASUDA TAKEYOSHI , HARADA SHIN , HONAGA MISAKO , WADA KEIJI , HIYOSHI TORU
IPC分类号： H01L29/12 , H01L21/336 , H01L29/06 , H01L29/78 , H01L29/861
CPC分类号： H01L29/66068 , H01L21/046 , H01L21/0475 , H01L21/3065 , H01L29/045 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/0657 , H01L29/0661 , H01L29/0696 , H01L29/1608 , H01L29/4236 , H01L29/6606 , H01L29/7397 , H01L29/7813 , H01L29/8613 , H01L29/868
摘要： Provided are a semiconductor device which can exhibit properties thereof steadily and has high quality and a process for producing the semiconductor device. The semiconductor device comprises a substrate (1) which has the main surface and silicon carbide layers (2-5) which are formed on the main surface of the substrate (1) and each of which has a side surface that is inclined against the main surface. The side surface substantially contains face [03-3-8]. The side surface contains a channel region.
摘要翻译：提供一种稳定地显示其性能并且具有高质量的半导体器件以及用于制造半导体器件的工艺。半导体器件包括：具有主表面的基板（1）和形成在基板（1）的主表面上的碳化硅层（2-5），并且每个基板具有与主体相反的侧表面表面。侧面基本上包含面[03-3-8]。侧面包含通道区域。

3. 发明申请

WO2012077443A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：WO2012077443A1
公开(公告)日：2012-06-14
申请号：PCT/JP2011075590
申请日：2011-11-07
申请人： SUMITOMO ELECTRIC INDUSTRIES , KUBOTA RYOSUKE , WADA KEIJI , MASUDA TAKEYOSHI , SHIOMI HIROMU
发明人： KUBOTA RYOSUKE , WADA KEIJI , MASUDA TAKEYOSHI , SHIOMI HIROMU
IPC分类号： H01L21/265 , H01L21/336 , H01L29/12 , H01L29/78
CPC分类号： H01L29/7802 , H01L21/046 , H01L21/268 , H01L29/1608 , H01L29/66068
摘要： A silicon carbide substrate having a surface is prepared. Impurity regions (123-125) are formed by carrying out ion implantation into the silicon carbide substrate through the surface. Annealing is carried out for the purpose of activating the impurity regions. The annealing comprises: a step for irradiating the surface of the silicon carbide substrate with first laser light that has a first wavelength; and a step for irradiating the surface of the silicon carbide substrate with second laser light that has a second wavelength. The silicon carbide substrate has first and second extinction coefficients respectively at the first and second wavelengths. The ratio of the first extinction coefficient to the first wavelength is larger than 5 × 105/m. The ratio of the second extinction coefficient to the second wavelength is smaller than 5 × 105/m. Consequently, damage to the surface of the silicon carbide substrate during the laser annealing can be reduced.
摘要翻译：制备具有表面的碳化硅衬底。杂质区域（123-125）通过经由表面对碳化硅基板进行离子注入而形成。退火是为了激活杂质区而进行的。退火包括：用具有第一波长的第一激光照射碳化硅衬底的表面的步骤; 以及用具有第二波长的第二激光照射碳化硅衬底的表面的步骤。碳化硅衬底分别在第一和第二波长处具有第一和第二消光系数。第一消光系数与第一波长的比率大于5×105 / m。第二消光系数与第二波长的比率小于5×105 / m。因此，可以减少激光退火过程中碳化硅衬底表面的损坏。

4. 发明申请

WO2012017958A1 PROCESS FOR PRODUCTION OF SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件制造工艺
公开(公告)号：WO2012017958A1
公开(公告)日：2012-02-09
申请号：PCT/JP2011067501
申请日：2011-07-29
申请人： SUMITOMO ELECTRIC INDUSTRIES , MASUDA TAKEYOSHI
发明人： MASUDA TAKEYOSHI
IPC分类号： H01L29/12 , H01L21/336 , H01L29/78
CPC分类号： H01L29/1608 , H01L21/0445 , H01L21/3065 , H01L29/045 , H01L29/0623 , H01L29/4236 , H01L29/66068 , H01L29/7397 , H01L29/7813 , H01L29/8613 , Y10S438/931
摘要： Provided is a process for producing a semiconductor device which can exhibit properties thereof steadily and has high quality. The process for producing a semiconductor device comprises the steps of: preparing a silicon carbide layer (2-4) having a main surface; removing a part of the silicon carbide layer (2-4) to form a groove (16) on the main surface; and removing a part of the side wall of the groove (16) by thermal etching.
摘要翻译：本发明提供一种能够稳定地显示其性能并且具有高质量的半导体器件的制造方法。制造半导体器件的方法包括以下步骤：制备具有主表面的碳化硅层（2-4）; 去除一部分碳化硅层（2-4）以在主表面上形成凹槽（16）; 并通过热蚀刻去除凹槽（16）的一部分侧壁。

5. 发明申请

WO2012017798A9 SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCTION THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2012017798A9
公开(公告)日：2013-01-10
申请号：PCT/JP2011066096
申请日：2011-07-14
申请人： SUMITOMO ELECTRIC INDUSTRIES , MASUDA TAKEYOSHI
发明人： MASUDA TAKEYOSHI
IPC分类号： H01L29/12 , H01L21/336 , H01L29/78
CPC分类号： H01L29/1608 , H01L21/0445 , H01L21/3065 , H01L29/045 , H01L29/0623 , H01L29/4236 , H01L29/66068 , H01L29/7397 , H01L29/7813 , H01L29/8613 , Y10S438/931
摘要： Provided are a semiconductor device which can exhibit properties thereof steadily and has high quality and a process for producing the semiconductor device. The semiconductor device comprises a substrate (1) which has the main surface and silicon carbide layers (2-5). The silicon carbide layers are formed on the main surface of the substrate (1). Each of the silicon carbide layers has a side surface which is an end surface that is inclined against the main surface. The side surface substantially contains either face [03-3-8] or face [01-1-4] when each of the silicon carbide layers is of a hexagonal crystal type, and substantially contains face [100] when each of the silicon carbide layers is of a cubic crystal type.
摘要翻译：提供一种稳定地显示其性能并且具有高质量的半导体器件以及用于制造半导体器件的工艺。半导体器件包括具有主表面和碳化硅层（2-5）的衬底（1）。碳化硅层形成在基板（1）的主表面上。每个碳化硅层具有侧表面，该侧表面是相对于主表面倾斜的端面。当每个碳化硅层为六方晶型时，侧表面基本上包含面[03-3-8]或面[01-1-4]，并且当每个碳化硅层是立方晶型。

6. 发明申请

WO2010134415A9 SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2010134415A9
公开(公告)日：2011-08-25
申请号：PCT/JP2010057112
申请日：2010-04-22
申请人： SUMITOMO ELECTRIC INDUSTRIES , WADA KEIJI , TAMASO HIDETO , MASUDA TAKEYOSHI , HONAGA MISAKO
发明人： WADA KEIJI , TAMASO HIDETO , MASUDA TAKEYOSHI , HONAGA MISAKO
IPC分类号： H01L21/28 , H01L21/336 , H01L21/337 , H01L21/768 , H01L29/12 , H01L29/417 , H01L29/78 , H01L29/808
CPC分类号： H01L21/0485 , H01L21/0455 , H01L29/1608 , H01L29/401 , H01L29/45 , H01L29/66068 , H01L29/7802 , H01L29/808
摘要： Disclosed is a silicon carbide semiconductor device which, when the electrode material is different from the material of the internal interconnects, eliminates the possibility of trouble at the contact interface of these different metals, and has high reliability even after long periods of use. The semiconductor device is provided with contact electrodes (16) which contact silicon carbide (14, 18), and interconnects (19) which connect with the contact electrodes. The contact electrodes (16) are formed from an alloy containing titanium, aluminum, and silicon. The interconnects (19) are formed either from aluminum or aluminum alloy and are connected with the contact electrodes by contacting the contact electrodes.
摘要翻译：公开了一种碳化硅半导体器件，当电极材料与内部互连的材料不同时，消除了在这些不同金属的接触界面处的麻烦的可能性，并且即使在长时间使用后也具有高可靠性。半导体器件具有接触碳化硅（14,18）的接触电极（16）和与接触电极连接的互连（19）。接触电极（16）由含有钛，铝和硅的合金形成。互连（19）由铝或铝合金形成，并通过接触电极与接触电极连接。

7. 发明申请

WO2014203645A1 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：WO2014203645A1
公开(公告)日：2014-12-24
申请号：PCT/JP2014062425
申请日：2014-05-09
申请人： SUMITOMO ELECTRIC INDUSTRIES
发明人： KUBOTA RYOSUKE , MASUDA TAKEYOSHI
IPC分类号： H01L21/336 , H01L21/265 , H01L21/266 , H01L29/12 , H01L29/78
CPC分类号： H01L29/1608 , H01L21/0415 , H01L21/046 , H01L21/0465 , H01L29/1095 , H01L29/167 , H01L29/66068 , H01L29/7395 , H01L29/7802
摘要： The present invention is provided with: a step (S10) for preparing a silicon carbide substrate, which has a first surface (main surface) (10a), and which includes a first impurity region (drift region) (12) having a first conductivity type; a step (S20) for forming an adjustment film (2) covering at least a part of the first surface (main surface) (10a), and a mask film (1) having an opening pattern from which at least a part of the adjustment film (2) is exposed; a step (S30) for forming, in the first impurity region (drift region) (12), a second impurity region (p body region) (13) having a second conductivity type by implanting an impurity from the first surface (main surface) (10a) via the adjustment film (2) using the mask film (1) as a mask; a step (S40) for removing at least a part of the adjustment film (2); and a step (S50) for forming, in the second impurity region (p body region) (13), a third impurity region (n+ source region) (14) having a first conductivity type by implanting an impurity from the first surface (main surface) (10a) using the mask film (1) as a mask. Consequently, a silicon carbide semiconductor device having a channel length controlled in a submicron order, and a method for manufacturing the silicon carbide semiconductor device are provided.
摘要翻译：本发明提供有：具有第一表面（主表面）（10a）的碳化硅衬底的制备步骤（S10），其包括具有第一导电性的第一杂质区（漂移区）（12）类型; 用于形成覆盖第一表面（主表面）（10a）的至少一部分的调整膜（2）的步骤（S20）和具有开口图案的掩模膜（1），至少部分调节膜（2）暴露; 通过从第一表面（主表面）注入杂质，在第一杂质区（漂移区）（12）中形成具有第二导电类型的第二杂质区（p体区）（13）的步骤（S30）（10a）经由所述调整膜（2）使用所述掩模膜（1）作为掩模; 用于去除所述调整膜（2）的至少一部分的步骤（S40）; 以及通过从第一表面（主体）注入杂质，在第二杂质区域（p体区域）（13）中形成具有第一导电类型的第三杂质区域（n +源极区域）（14）的步骤（S50）表面）（10a），使用掩模膜（1）作为掩模。因此，提供了具有以亚微米级控制的通道长度的碳化硅半导体器件，以及制造碳化硅半导体器件的方法。

8. 发明专利

DE112014005127T5 Siliziumkarbid-Halbleitervorrichtung und Verfahren zur Herstellung derselben 未知
公开(公告)号：DE112014005127T5
公开(公告)日：2016-08-11
申请号：DE112014005127
申请日：2014-09-18
申请人： RENESAS ELECTRONICS CORP , SUMITOMO ELECTRIC INDUSTRIES
发明人： YAMADA SHUNSUKE , HORII TAKU , MASUDA TAKEYOSHI , TANAKA SO , KOBAYASHI MASAYUKI , KUBOTA RYOSUKE , HAMAJIMA DAISUKE , KIMURA SHINJI
IPC分类号： H01L21/336 , H01L21/28 , H01L21/66 , H01L29/12 , H01L29/423 , H01L29/49 , H01L29/78
摘要： Eine Siliziumkarbid-Halbleitervorrichtung weist ein Siliziumkarbid-Substrat (10), einen Gate-Isolierfilm (15) und eine Gate-Elektrode (27) auf. Das Siliziumkarbid-Substrat (10) weist eine erste Hauptfläche (10a) und eine zweite Hauptfläche (10b) gegenüber der ersten Hauptfläche (10a) auf. Der Gate-Isolierfilm (15) ist in Kontakt mit der ersten Hauptfläche (10a) des Siliziumkarbid-Substrats (10) vorgesehen. Die Gate-Elektrode (27) ist auf dem Gate-Isolierfilm (15) vorgesehen, so dass der Gate-Isolierfilm (15) zwischen der Gate-Elektrode (27) und dem Siliziumkarbid-Substrat (10) liegt. In einem ersten Belastungstest, in dem für 100 Stunden eine Gate-Spannung von –5 V bei einer Temperatur von 175°C an die Gate-Elektrode (27) angelegt ist, beträgt ein Absolutwert einer Differenz zwischen einer ersten Schwellenspannung und einer zweiten Schwellenspannung nicht mehr als 0,5 V, wobei eine Schwellenspannung vor dem ersten Belastungstest als die erste Schwellenspannung und eine Schwellenspannung nach dem ersten Belastungstest als die zweite Schwellenspannung definiert sind. Somit können eine Siliziumkarbid-Halbleitervorrichtung mit verringerten Schwellenspannungsschwankungen und ein Verfahren zur Herstellung derselben bereitgestellt werden.

9. 发明专利

DE112013003093T5 Messvorrichtung, Messverfahren und Elementherstellungsverfahren unter Verwendung des Messverfahrens 未知
公开(公告)号：DE112013003093T5
公开(公告)日：2015-03-12
申请号：DE112013003093
申请日：2013-07-09
申请人： SUMITOMO ELECTRIC INDUSTRIES
发明人： SAKAI MITSUHIKO , MASUDA TAKEYOSHI , HIRATSUKA KENJI
IPC分类号： H01L21/66 , G01R31/26
摘要： Eine Messvorrichtung umfasst: einen Messfühler (1) zum Anlegen einer Spannung an eine Elektrode eines Elements; und ein Zufuhrelement (2), das einem Kontaktabschnitt (10C) zwischen der Elektrode und dem Messfühler (1) durch eine Oberfläche des Messfühlers (1) eine Isolierflüssigkeit (20) zuführt. Dementsprechend kann die Isolierflüssigkeit (20) dem Kontaktabschnitt (10C) zwischen der Elektrode und der Messfühler (1) durch die Oberfläche des Messfühler (1), die relativ zu der Elektrode angeordnet ist, zuverlässig zugeführt werden.

10. 发明专利

CA2797024A1 SILICON CARBIDE SEMICONDUCTOR DEVICE 未知
公开(公告)号：CA2797024A1
公开(公告)日：2012-10-11
申请号：CA2797024
申请日：2012-01-27
申请人： SUMITOMO ELECTRIC INDUSTRIES
发明人： MASUDA TAKEYOSHI , HIYOSHI TORU , WADA KEIJI
IPC分类号： H01L29/12 , H01L21/3065 , H01L21/336 , H01L29/78
摘要： A silicon carbide layer is epitaxially formed on a principal surface of a substrate (1). A groove having a side wall (6) that is inclined with respect to the principal surface is furnished in the silicon carbide layer. The side wall (6) has an off angle of 50º-65º with respect to the {0001} plane. A gate insulating film (8) is furnished over the side wall (6) of the silicon carbide layer. The silicon carbide layer includes a body region (3) facing a gate electrode (9) with the gate insulating film (8) therebetween, and having a first conduction type; and a pair of regions (2, 4) separated from one another by the body region (3), and having a second conduction type. The body region (3) has an impurity density of 5 × 1016cm-3 or greater. The degree of freedom in setting the threshold voltage can thereby be increased, while decline of channel mobility is minimized.

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