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1. 发明申请

WO2006011222A8 SEMICONDUCTOR DEVICE AND WRITING METHOD 审中-公开
标题翻译：半导体器件和写入方法
公开(公告)号：WO2006011222A8
公开(公告)日：2006-03-16
申请号：PCT/JP2004010914
申请日：2004-07-30
申请人： SPANSION LLC , SPANSION JAPAN LTD , YAMADA SHIGEKAZU
发明人： YAMADA SHIGEKAZU
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/10 , G11C2216/14
摘要： A semiconductor device comprising a memory cell array including multi-valued memory cells each having a plurality of different threshold values; a first latch circuit for latching information in input information of multi-words; a second latch circuit for latching write information obtained by converting the information in the input information of the multi-words to information that are in accordance with the levels of the multi-valued memory cells; a write circuit for writing the information into the multi-valued memory cells for each group corresponding to the number of memory cells into which the information can be simultaneously written;and a control circuit for controlling the writing into the memory cell array. Thus, information are simultaneously written for each of the groups into which the input information of the multi-words are divided, so that the write time per unit word can be substantially shortened. In this way, during the writing into the multi-valued memory cells, even if programs and verifications must be repeated many times, the write time does not increase.
摘要翻译：一种半导体器件，包括具有多值存储单元的存储单元阵列，每个多值存储单元具有多个不同的阈值; 用于在多字输入信息中锁存信息的第一锁存电路; 第二锁存电路，用于锁存通过将多字的输入信息中的信息转换为与多值存储器单元的电平相对应的信息而获得的写入信息; 写入电路，用于将信息写入与可以同时写入信息的存储单元的数量相对应的每个组的多值存储单元;以及控制电路，用于控制对存储单元阵列的写入。因此，对于分割多字的输入信息的每个组同时写入信息，从而可以显着缩短每单位字的写入时间。以这种方式，在写入多值存储器单元期间，即使程序和验证必须重复多次，写入时间也不会增加。

2. 发明专利

DE112004002927B4 Halbleiterbauelement und Verfahren zum Beschreiben desselben 未知
公开(公告)号：DE112004002927B4
公开(公告)日：2011-07-21
申请号：DE112004002927
申请日：2004-07-30
申请人： SPANSION LLC N D GES D STAATES DELAWARE , SPANSION JAPAN LTD
发明人： YAMADA SHIGEKAZU
IPC分类号： G11C16/10
摘要： Halbleiterbauelement mit: einer ersten Zwischenspeicherschaltung, die Schreibinformation aus mehreren Wörtern speichert, in die eine Mehrworteingangsinformation auf der Grundlage von Pegeln einer Mehrpegelspeicherzelle umgewandelt wird; und einer Schreibschaltung, die die Schreibinformation aus mehreren Wörtern auf Grundlage einzelner Gruppen schreibt, wobei eine einzelne Gruppe mehreren gleichzeitig programmierbaren Speicherzellen zugeordnet ist.

3. 发明专利

JP2010267382A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010267382A
公开(公告)日：2010-11-25
申请号：JP2010195775
申请日：2010-09-01
申请人： Spansion Japan株式会社 , Spansion Japan Ltd , Spansion Llc , スパンションエルエルシー
发明人： YAMADA SHIGEKAZU
IPC分类号： G11C16/02 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that prevents erasure in program operation. SOLUTION: The semiconductor device has: a memory part including a memory cell having a plurality of different thresholds; a read circuit reading out existing data from a memory cell in which input write data is to be written by using a sense amplifier for verify; and a detecting circuit comparing the write data with the existing data and detecting a pattern in which erasure occurs in write operation. The pattern that causes erasure in write operation is prohibited. When the prohibition operation is recognized, the operation is forcibly terminated without starting write operation by a write command. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种防止编程操作中的擦除的半导体器件。解决方案：半导体器件具有：存储器部分，其包括具有多个不同阈值的存储单元; 读取电路通过使用用于验证的读出放大器从要存储输入写数据的存储单元读出现有数据; 以及检测电路，将写入数据与现有数据进行比较，并检测在写入操作中发生擦除的模式。禁止在写操作中导致擦除的模式。当禁止操作被识别时，操作被强制终止，而不用写入命令开始写入操作。版权所有（C）2011，JPO＆INPIT

4. 发明专利

GB2431026B Semiconductor device and writing method 未知
公开(公告)号：GB2431026B
公开(公告)日：2008-05-07
申请号：GB0701433
申请日：2004-07-30
申请人： SPANSION LLC , SPANSION JAPAN LTD
发明人： YAMADA SHIGEKAZU
IPC分类号： G11C16/10 , G11C7/10 , G11C11/56 , G11C16/04

5. 发明专利

DE112004002927T5 未知
公开(公告)号：DE112004002927T5
公开(公告)日：2008-03-20
申请号：DE112004002927
申请日：2004-07-30
申请人： SPANSION LLC N D GES D STAATES , SPANSION JAPAN LTD
发明人： YAMADA SHIGEKAZU
IPC分类号： G11C16/10

6. 发明专利

GB2431026A Semiconductor device and writing method 未知
公开(公告)号：GB2431026A
公开(公告)日：2007-04-11
申请号：GB0701433
申请日：2004-07-30
申请人： SPANSION LLC , SPANSION JAPAN LTD
发明人： YAMADA SHIGEKAZU
IPC分类号： G11C16/10 , G11C7/10 , G11C11/56 , G11C16/04
摘要： A semiconductor device comprising a memory cell array including multi-valued memory cells each having a plurality of different threshold values; a first latch circuit for latching information in input information of multi-words; a second latch circuit for latching write information obtained by converting the information in the input information of the multi-words to information that are in accordance with the levels of the multi-valued memory cells; a write circuit for writing the information into the multi-valued memory cells for each group corresponding to the number of memory cells into which the information can be simultaneously written; and a control circuit for controlling the writing into the memory cell array. Thus, information are simultaneously written for each of the groups into which the input information of the multi-words are divided, so that the write time per unit word can be substantially shortened. In this way, during the writing into the multi-valued memory cells, even if programs and verifications must be repeated many times, the write time does not increase.

7. 发明公开

EP1729305A4 SEMICONDUCTOR DEVICE AND METHOD FOR WRITING DATA IN SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体部件和方法将数据写入到半导体元件
公开(公告)号：EP1729305A4
公开(公告)日：2007-08-22
申请号：EP04723724
申请日：2004-03-26
申请人： SPANSION LLC , SPANSION JAPAN LTD
发明人： YAMADA SHIGEKAZU
IPC分类号： G11C16/10 , G11C11/34 , G11C11/56 , G11C16/22 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454
摘要： A semiconductor device comprising a memory section including a plurality of memory cells having different threshold values, a circuit for reading out existing data from a memory cell into which inputted writing data is written, and a circuit for detecting such a pattern that allows a writing operation to start an erase operation by comparing the writing data with the existing data in the memory cell. The pattern that triggers an erase operation by using a writing operation is regarded as a prohibition operation, and, when the prohibition operation is recognized, a writing operation by a writing command is not started but the operation is ended forcibly. Consequently, such a phenomenon that erase is caused by a program operation can be avoided.

8. 发明申请

WO2008024688A2 METHOD, APPARATUS AND SYSTEM RELATING TO AUTOMATIC CELL THRESHOLD VOLTAGE MEASUREMENT 审中-公开
标题翻译：方法，与自动电池电压测量相关的装置和系统
公开(公告)号：WO2008024688A2
公开(公告)日：2008-02-28
申请号：PCT/US2007076246
申请日：2007-08-17
申请人： MICRON TECHNOLOGY INC , YAMADA SHIGEKAZU
发明人： YAMADA SHIGEKAZU
CPC分类号： G11C29/50 , G11C16/04 , G11C16/0483 , G11C16/28 , G11C29/12005 , G11C29/50004
摘要： Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current generator, a plurality of memory cells, a pre charge bit line reference circuit, and comparator and latch circuitry. If the reference current is greater than the memory cell current, the bit line voltage will increase. Conversely, if the reference current is less than the memory cell current, the bit line voltage will decrease. The reference current is generated in large steps until a comparator, that compares the bit line voltage and a pre charged bit line reference voltage, is switched. The reference current then generates a current in small steps until the comparator is again switched. The reference current converges on the memory cell current within an accuracy of 10nA. The memory cell threshold voltage is then determined from the memory cell current. Systems including memory according to an embodiment of the invention are also disclosed.
摘要翻译：公开了用于自动测量存储单元阈值电压的方法和装置。测量电路包括内部参考电流发生器，多个存储单元，预充电位线参考电路以及比较器和锁存电路。如果参考电流大于存储单元电流，则位线电压将增加。相反，如果参考电流小于存储单元电流，则位线电压将降低。参考电流以大的步长产生，直到比较位线电压和预充电位线参考电压的比较器被切换为止。参考电流然后以小步骤产生电流，直到再次切换比较器。参考电流在10nA的精度内收敛于存储单元电流。然后从存储单元电流确定存储单元阈值电压。还公开了包括根据本发明的实施例的存储器的系统。

9. 发明申请

WO2010141304A3 MEMORY ERASE METHODS AND DEVICES 审中-公开
标题翻译：记忆删除方法和设备
公开(公告)号：WO2010141304A3
公开(公告)日：2011-02-10
申请号：PCT/US2010036316
申请日：2010-05-27
申请人： MICRON TECHNOLOGY INC , YAMADA SHIGEKAZU , TANAKA TOMOHARU
发明人： YAMADA SHIGEKAZU , TANAKA TOMOHARU
IPC分类号： G11C16/14 , G11C7/24 , G11C16/16 , G11C16/30
CPC分类号： G11C16/16 , G11C16/30
摘要： Memory devices and erase methods for memories are disclosed, such as those adapted to discharge an erase voltage from a memory block while protecting low voltage string select gate transistors by maintaining the string select gate transistors in a turned on state during discharge.
摘要翻译：公开了用于存储器的存储器件和擦除方法，例如适于从存储器块放电擦除电压的存储器件和擦除方法，同时通过在放电期间将串选择栅极晶体管保持在导通状态来保护低压串选择栅极晶体管。

10. 发明申请

WO2008024688B1 METHOD, APPARATUS AND SYSTEM RELATING TO AUTOMATIC CELL THRESHOLD VOLTAGE MEASUREMENT 审中-公开
标题翻译：与自动单元阈值电压测量相关的方法，装置和系统
公开(公告)号：WO2008024688B1
公开(公告)日：2008-07-17
申请号：PCT/US2007076246
申请日：2007-08-17
申请人： MICRON TECHNOLOGY INC , YAMADA SHIGEKAZU
发明人： YAMADA SHIGEKAZU
IPC分类号： G11C29/50
CPC分类号： G11C29/50 , G11C16/04 , G11C16/0483 , G11C16/28 , G11C29/12005 , G11C29/50004
摘要： Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current generator (212), a plurality of memory cells (114), a pre charge bit line reference circuit (21§8), and comparator (220) and latch circuitry (222). If the reference current is greater than the memory cell current, the bit line voltage will increase. Conversely, if the reference current is less than the memory cell current, the bit line voltage will decrease. The reference current is generated in large steps until a comparator, that compares the bit line voltage and a pre charged bit line reference voltage, is switched. The reference current then generates a current in small steps until the comparator is again switched. The reference current converges on the memory cell current within an accuracy of 1OnA. The memory cell threshold voltage is then determined from the memory cell current. Systems including memory according to an embodiment of the invention are also disclosed.
摘要翻译：公开了用于自动测量存储单元阈值电压的方法和设备。测量电路包括内部参考电流发生器（212），多个存储器单元（114），预充电位线参考电路（21§8）以及比较器（220）和锁存电路（222）。如果参考电流大于存储单元电流，则位线电压将增加。相反，如果参考电流小于存储单元电流，则位线电压将降低。基准电流以较大的步长产生，直到比较位线电压和预充电位线参考电压的比较器被切换。参考电流然后以小的步幅产生电流，直到再次开关比较器。参考电流在10nA的精度内收敛于存储器单元电流。然后从存储单元电流确定存储单元阈值电压。还公开了包括根据本发明实施例的存储器的系统。

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