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1. 发明申请

US20110248326A1 STRUCTURE AND METHOD TO INTEGRATE EMBEDDED DRAM WITH FINFET 有权
标题翻译：用FINFET整合嵌入式DRAM的结构和方法
公开(公告)号：US20110248326A1
公开(公告)日：2011-10-13
申请号：US12755487
申请日：2010-04-07
申请人： SIVANANDA KANAKASABAPATHY , Hemanth Jagannathan , Geng Wang
发明人： SIVANANDA KANAKASABAPATHY , Hemanth Jagannathan , Geng Wang
IPC分类号： H01L27/108 , H01L21/28
CPC分类号： H01L27/10826 , H01L21/26586 , H01L21/845 , H01L27/10879 , H01L27/10891 , H01L27/1211
摘要： A transistor includes a first fin structure and at least a second fin structure formed on a substrate. A deep trench area is formed between the first and second fin structures. The deep trench area extends through an insulator layer of the substrate and a semiconductor layer of the substrate. A high-k metal gate is formed within the deep trench area. A polysilicon layer is formed within the deep trench area adjacent to the metal layer. The polysilicon layer and the high-k metal layer are recessed below a top surface of the insulator layer. A poly strap in the deep trench area is formed on top of the high-k metal gate and the polysilicon material. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first fin structure and the second fin structure are electrically coupled to the poly strap.
摘要翻译：晶体管包括第一鳍结构和形成在衬底上的至少第二鳍结构。在第一和第二翅片结构之间形成深沟槽区域。深沟槽区域延伸穿过衬底的绝缘体层和衬底的半导体层。在深沟槽区域内形成高k金属栅极。在与金属层相邻的深沟槽区域内形成多晶硅层。多晶硅层和高k金属层凹陷在绝缘体层的顶表面下方。深沟槽区域中的多晶带形成在高k金属栅极和多晶硅材料的顶部上。该多晶带的尺寸设计成在第一和第二鳍结构的顶表面下方。第一翅片结构和第二翅片结构电耦合到多晶带。

2. 发明申请

US20110212548A1 METHOD FOR SEMICONDUCTOR GATE HARDMASK REMOVAL AND DECOUPLING OF IMPLANTS 有权
标题翻译：用于半导体闸门去除和去除植入物的方法
公开(公告)号：US20110212548A1
公开(公告)日：2011-09-01
申请号：US12714702
申请日：2010-03-01
申请人： SIVANANDA KANAKASABAPATHY , HEMANTH JAGANNATHAN
发明人： SIVANANDA KANAKASABAPATHY , HEMANTH JAGANNATHAN
IPC分类号： H01L21/336 , H01L21/66
CPC分类号： H01L29/4908 , H01L29/66772
摘要： A method is provided for fabricating a semiconductor device having implanted source/drain regions and a gate region, the gate region having been masked by the gate hardmask during source/drain implantation, the gate region having a polysilicon gate layered on a metal layered on a high-K dielectric layer. The gate region and the source/drain regions may be covered with a self planarizing spin on film. The film may be blanket etched back to uncover the gate hardmask while maintaining an etched back self planarizing spin on film on the implanted source/drain regions. The gate hardmask may be etched back while the etched back film remains in place to protect the implanted source/drain regions. The gate region may be low energy implanted to lower sheet resistance of the polysilicon layer. The etched back film may be then removed.
摘要翻译：提供了一种用于制造具有注入的源极/漏极区域和栅极区域的半导体器件的方法，栅极区域在源极/漏极注入期间被栅极硬掩模掩蔽，栅极区域具有分层在金属上的金属上的多晶硅栅极高K电介质层。栅极区域和源极/漏极区域可以用膜上的自平面旋转覆盖。该膜可以被覆盖回蚀刻以露出栅极硬掩模，同时保持在植入的源极/漏极区域上的膜上的回蚀刻自平坦化自旋。栅极硬掩模可以被蚀刻回来，同时蚀刻的后膜保持在适当位置以保护植入的源极/漏极区域。栅极区域可以是低能量注入以降低多晶硅层的薄层电阻。然后可以去除蚀刻后的膜。

3. 发明申请

US20110108921A1 SINGLE METAL GATE CMOS INTEGRATION BY INTERMIXING POLARITY SPECIFIC CAPPING LAYERS 有权
标题翻译：单金属栅极CMOS集成通过界面极化特定的覆盖层
公开(公告)号：US20110108921A1
公开(公告)日：2011-05-12
申请号：US12616941
申请日：2009-11-12
申请人： SIVANANDA KANAKASABAPATHY , Hemanth Jagannathan , Matthew Copel
发明人： SIVANANDA KANAKASABAPATHY , Hemanth Jagannathan , Matthew Copel
IPC分类号： H01L27/092 , H01L21/306
CPC分类号： H01L21/3105 , H01L21/823842
摘要： A method for forming a complementary metal oxide semiconductor device includes forming a first capping layer on a dielectric layer, blocking portions in the capping layer in regions where the capping layer is to be preserved using a block mask. Exposed portions of the first capping layer are intermixed with the dielectric layer to form a first intermixed layer. The block mask is removed. The first capping layer and the first intermixed layer are etched such that the first capping layer is removed to re-expose the dielectric layer in regions without removing the first intermixed layer.
摘要翻译：用于形成互补金属氧化物半导体器件的方法包括在电介质层上形成第一覆盖层，使用阻挡掩模阻挡覆盖层在要被保持的区域中的部分。第一覆盖层的暴露部分与电介质层混合以形成第一混合层。去除块掩模。蚀刻第一覆盖层和第一混合层，使得除去第一覆盖层以在不去除第一混合层的情况下再次暴露在区域中的电介质层。

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