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1. 发明申请

WO0243319A2 COMMUNICATIONS ARCHITECTURE FOR STORAGE-BASED DEVICES 审中-公开
标题翻译：基于存储设备的通信架构
公开(公告)号：WO0243319A2
公开(公告)日：2002-05-30
申请号：PCT/US0143474
申请日：2001-11-21
申请人： SILICON IMAGE , SHIN YESHIK , LEE DAVID D , JEONG DEOG KYOON , KONG SHING , LEE DONGYUN
发明人： SHIN YESHIK , LEE DAVID D , JEONG DEOG-KYOON , KONG SHING , LEE DONGYUN
IPC分类号： H04J99/00 , G06F12/00 , G11C8/00 , H03M5/00 , H03M13/00 , H04J1/16 , H04J3/06 , H04J3/12 , H04J3/16 , H04J3/22 , H04L1/00 , H04L7/00 , H04L12/00 , H04L12/28 , H04L12/56 , H04L29/06
CPC分类号： H04L47/10 , H04L47/245 , H04L47/34 , H04L47/365
摘要： A serial comminications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network such as a storage area network. The Storage link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of comunications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.
摘要翻译：用于在主机和数据存储设备之间进行通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。存储链路架构可以基于分组类型，分组的动态分段，不对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如以下更详细地描述的。存储链路架构还可以指定编码技术来优化转换并确保直流平衡。

2. 发明申请

WO0243319A9 COMMUNICATIONS ARCHITECTURE FOR STORAGE-BASED DEVICES 审中-公开
标题翻译：基于存储设备的通信架构
公开(公告)号：WO0243319A9
公开(公告)日：2004-04-01
申请号：PCT/US0143474
申请日：2001-11-21
申请人： SILICON IMAGE , SHIN YESHIK , LEE DAVID D , JEONG DEOG-KYOON , KONG SHING , LEE DONGYUN
发明人： SHIN YESHIK , LEE DAVID D , JEONG DEOG-KYOON , KONG SHING , LEE DONGYUN
IPC分类号： H04J99/00 , G06F12/00 , G11C8/00 , H03M5/00 , H03M13/00 , H04J1/16 , H04J3/06 , H04J3/12 , H04J3/16 , H04J3/22 , H04L1/00 , H04L7/00 , H04L12/00 , H04L12/28 , H04L12/56 , H04L29/06
CPC分类号： H04L47/10 , H04L47/245 , H04L47/34 , H04L47/365
摘要： A serial comminications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network such as a storage area network. The Storage link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of comunications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.
摘要翻译：用于在主机和数据存储设备之间进行通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。存储链路架构可以基于分组类型，分组的动态分段，不对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如以下更详细地描述的。存储链路架构还可以指定编码技术来优化转换并确保直流平衡。

3. 发明申请

WO0243319A8 COMMUNICATIONS ARCHITECTURE FOR STORAGE-BASED DEVICES 审中-公开
标题翻译：基于存储设备的通信架构
公开(公告)号：WO0243319A8
公开(公告)日：2003-04-17
申请号：PCT/US0143474
申请日：2001-11-21
申请人： SILICON IMAGE , SHIN YESHIK , LEE DAVID D , JEONG DEOG-KYOON , KONG SHING , LEE DONGYUN
发明人： SHIN YESHIK , LEE DAVID D , JEONG DEOG-KYOON , KONG SHING , LEE DONGYUN
IPC分类号： H04J99/00 , G06F12/00 , G11C8/00 , H03M5/00 , H03M13/00 , H04J1/16 , H04J3/06 , H04J3/12 , H04J3/16 , H04J3/22 , H04L1/00 , H04L7/00 , H04L12/00 , H04L12/28 , H04L12/56 , H04L29/06
CPC分类号： H04L47/10 , H04L47/245 , H04L47/34 , H04L47/365
摘要： A serial comminications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network such as a storage area network. The Storage link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of comunications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.
摘要翻译：用于在主机和数据存储设备之间进行通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。存储链路架构可以基于分组类型，分组的动态分段，不对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如以下更详细地描述的。存储链路架构还可以指定编码技术来优化转换并确保直流平衡。

4. 发明专利

DE69531567D1 未知
公开(公告)号：DE69531567D1
公开(公告)日：2003-10-02
申请号：DE69531567
申请日：1995-06-01
申请人： JEONG DEOG-KYOON , SUN MICROSYSTEMS INC
发明人： JEONG DEOG-KYOON
IPC分类号： H04L5/22 , H03K19/0185 , H03L7/089 , H03L7/099 , H03M9/00 , H04J3/04 , H04L5/14 , H04L7/00 , H04L7/033 , H04L13/10 , H04L25/02 , H04L25/08 , H04L29/10 , G06F13/40 , G06F1/06
摘要： A system for converting between parallel data and serial data is described. In the system, individual bits of the parallel data are latched into individual registers. Each register is coupled to a corresponding AND gate which is also connected to receive phased clock signals. The output terminals of the AND gates are connected to an OR gate. Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

5. 发明专利

DE69531567T2 未知
公开(公告)号：DE69531567T2
公开(公告)日：2004-06-24
申请号：DE69531567
申请日：1995-06-01
申请人： JEONG DEOG-KYOON , SUN MICROSYSTEMS INC
发明人： JEONG DEOG-KYOON
IPC分类号： H04L5/22 , H03K19/0185 , H03L7/089 , H03L7/099 , H03M9/00 , H04J3/04 , H04L5/14 , H04L7/00 , H04L7/033 , H04L13/10 , H04L25/02 , H04L25/08 , H04L29/10 , G06F13/40 , G06F1/06
摘要： A system for converting between parallel data and serial data is described. In the system, individual bits of the parallel data are latched into individual registers. Each register is coupled to a corresponding AND gate which is also connected to receive phased clock signals. The output terminals of the AND gates are connected to an OR gate. Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

6. 发明专利

JP2008148346A Adaptive bandwidth phase locked loop with feedforward divider 有权
标题翻译：自适应带宽相位锁定环路带有前置分路器
公开(公告)号：JP2008148346A
公开(公告)日：2008-06-26
申请号：JP2007341739
申请日：2007-12-11
申请人： Silicon Image Inc , シリコンイメージ,インコーポレイテッド
发明人： KIM JAEHA , JEONG DEOG-KYOON
IPC分类号： H03L7/22 , H03L7/10
CPC分类号： H03L7/23 , H03L7/0895 , H03L7/093 , H03L7/0995
摘要： PROBLEM TO BE SOLVED: To solve the problem of the reduction in a ring VCO frequency range, while the usable range of a VCO control voltage has shrunk considerably as a supply voltage has scaled below 1.2 V (volts) and a PLL application space continues to expand, demanding even wider frequency range from a single PLL.
SOLUTION: A chip includes first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals, and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second frequency division rates. The chip also includes phase locked loop control circuitry to select the first and second frequency division rates.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了解决环形VCO频率范围的减小的问题，当VCO控制电压的可用范围随着电源电压已经低于1.2V（伏特）而减小，并且PLL应用空间不断扩大，从单个PLL要求甚至更宽的频率范围。解决方案：芯片包括包括第一和第二压控振荡器（VCO）的第一和第二子锁相环（子PLL），以提供第一和第二VCO输出信号;以及第一和第二前馈分频器电路，用于将第一和第二压控振荡器通过第一和第二分频率，第一和第二VCO输出信号的第二频率。该芯片还包括用于选择第一和第二分频率的锁相环控制电路。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2007129735A Clock edge modulated serial link including dc balance control 有权
标题翻译：时钟边缘调制串行链路，包括直流平衡控制
公开(公告)号：JP2007129735A
公开(公告)日：2007-05-24
申请号：JP2006322567
申请日：2006-10-31
申请人： Silicon Image Inc , シリコンイメージ,インコーポレイテッド
发明人： KIM GYUDONG , CHOE WON JUN , JEONG DEOG-KYOON , KIM JAEHA , LEE BONG-JOON , KIM MIN-KYU
IPC分类号： H04L27/00
CPC分类号： H04L7/0008 , H04L25/0272 , H04L25/0284 , H04L25/4902
摘要： PROBLEM TO BE SOLVED: To provide a serial channel for supporting clocks, data and control signals such as DC balancing control signals to a low power mobile device. SOLUTION: A battery powered computing device has a channel arranged as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is arranged to apply clock edge modulated signals to the channel, wherein the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is arranged to recover the direct current balancing control signals. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供用于向低功率移动设备支持诸如DC平衡控制信号的时钟，数据和控制信号的串行通道。解决方案：电池供电的计算设备具有排列成单个直流平衡差分通道的通道。信号发射器连接到通道。信号发射机被布置成将时钟边缘调制信号施加到信道，其中时钟边缘调制信号包括直流平衡控制信号。信号接收器连接到通道。信号接收器被布置成恢复直流平衡控制信号。版权所有（C）2007，JPO＆INPIT

8. 发明申请

WO0016302A8 METHOD AND APPARATUS FOR BIDIRECTIONAL DATA TRANSFER BETWEEN A DIGITAL DISPLAY AND A COMPUTER 审中-公开
标题翻译：用于数字显示和计算机之间的双向数据传输的方法和装置
公开(公告)号：WO0016302A8
公开(公告)日：2001-02-08
申请号：PCT/US9920475
申请日：1999-09-10
申请人： SILICON IMAGE INC
发明人： KIM SUNGJOON , JEONG DEOG-KYOON , LEE DAVID D
IPC分类号： G06F3/14 , G09G1/16 , H04L5/14
CPC分类号： H04L5/14 , G06F3/14 , G09G1/16 , G09G2370/045
摘要： A new scheme to transfer bidirectional data streams between a digital display and a computer is disclosed. This bidirectional data transfer can make several I/O devices attach to a display. Existing digital display interfaces are usually unidirectional from a computing to a display. Due to the nature of the existing clocking scheme, backward data transfer from the display side to the computer requires a backward clock. This invention discloses a scheme to send data bidirectionally without sending the additional backward clock. This invention also discloses a scheme to tolerate jitters from the clock source. With this approach, this new interface can make a digital display an I/O concentrator.
摘要翻译：公开了一种在数字显示器和计算机之间传输双向数据流的新方案。这种双向数据传输可以使多个I / O设备连接到显示器。现有的数字显示接口通常是从计算到显示的单向的。由于现有的时钟方案的性质，从显示侧到计算机的反向数据传输需要一个反向时钟。本发明公开了一种双向发送数据的方案，而不发送额外的反向时钟。本发明还公开了一种允许来自时钟源的抖动的方案。通过这种方式，这个新界面可以使数字显示器成为一个I / O集中器。

9. 发明申请

WO9938281A9 SPREAD SPECTRUM PHASE MODULATION FOR SUPPRESSION OF ELECTROMAGNETIC INTERFERENCE IN PARALLEL DATA CHANNELS 审中-公开
标题翻译：用于抑制并行数据通道中电磁干扰的传播频谱相位调制
公开(公告)号：WO9938281A9
公开(公告)日：1999-11-04
申请号：PCT/US9901246
申请日：1999-01-20
申请人： SILICON IMAGE INC
发明人： MOON YONGSAM , JEONG DEOG-KYOON , KIM GYUDONG
IPC分类号： G06F1/04 , H04B1/707 , H04B15/00 , H04B15/04
CPC分类号： H04B1/707 , G06F1/04 , H04B15/00 , H04B15/04 , H04B2215/064
摘要： A new spread spectrum phase modulation (SSPM) technique is applicable to both data and clock signals. The SSPM technique is more suitable to board level designs than the direct-sequence spread spectrum (DSSS) technique. In addition, SSPM may be combined with controlled edge rate signaling to outperform DSSS.
摘要翻译：新的扩频相位调制（SSPM）技术适用于数据和时钟信号。 SSPM技术比直接序列扩频（DSSS）技术更适合板级设计。此外，SSPM可以与受控边缘速率信令组合以优于DSSS。

10. 发明申请

WO9840873A2 SYSTEM AND METHOD FOR DRIVING COLUMNS OF AN ACTIVE MATRIX DISPLAY 审中-公开
标题翻译：用于驱动活动矩阵显示的柱的系统和方法
公开(公告)号：WO9840873A2
公开(公告)日：1998-09-17
申请号：PCT/US9804767
申请日：1998-03-10
申请人： SILICON IMAGE INC
发明人： JEONG DEOG-KYOON , KIM GYUDONG , SONG HO YOUNG , LEE DAVID D
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
CPC分类号： G09G3/2011 , G09G3/3688 , G09G3/3696 , G09G2310/027
摘要： Described is a system and method for driving columns of an active matrix display using a resistor-string digital-to-analog converter (DAC). The description includes an auto-stop buffer circuit that drives an analog data voltage in two steps; the first step being active buffering by a "dead-zone amplifier" before the output reaches a certain level and the second step being acting as a passive conduit after the output reaches the certain level. The dead-zone amplifier inherently turns itself off when the analog voltage reaches the certain level. Also described are various column driver architectures in which buffers are placed in various ways in a column driver in between the resistor-string DAC and the column decoders in order to minimize the number of required buffers.
摘要翻译：描述了一种使用电阻串数模转换器（DAC）驱动有源矩阵显示器列的系统和方法。该描述包括以两步驱动模拟数据电压的自动停止缓冲电路; 第一步是在输出达到一定水平之前由“死区放大器”进行主动缓冲，第二步在输出达到一定水平之后作为无源导管。当模拟电压达到一定水平时，死区放大器本身就会自动关闭。还描述了各种列驱动器架构，其中缓冲器以各种方式放置在电阻器串DAC和列解码器之间的列驱动器中，以便使所需缓冲器的数量最小化。

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