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    • 5. 发明专利
    • Fundamental-frequency taking-out circuit
    • 基本频率采样电路
    • JPS6144330A
    • 1986-03-04
    • JP16607884
    • 1984-08-08
    • Seiko Instr & Electronics Ltd
    • SAKATA TOSHIOOBARA NOBUOONO KENICHIYAGI SHIGEKI
    • G10H1/00G01H3/04G01H3/08G10L11/00G10L11/04
    • G01H3/08
    • PURPOSE:To take the fundamental frequency out of signals having many harmonic components such as speech in real time, by comparing the positive and negative peaks of the signal with the positive and negative values of an input signal, and controlling a flip-flop. CONSTITUTION:A speech signal or a musical sound signal is inputted to peak detecting circuits 3 and 4, to which a DC potential is applied from a DC bias circuit 6, through inverted amplifiers 1 and 2, to which a DC potential is applied to a DC bias circuit 5. The peak value is held by a capacitor C. When the waveform indicates the peak value, the output of a comparator is inverted. An SRF/ F7 is set at the positive peak and reset at the negative peak. The Q output of the SRF/F7 is inputted to a differentiating circuit 8 and a delay circuit 9. When the positive peak is generated, a counter 11, which is counting a clock signal, is reset. The value immediately before is held by a latch circuit 12. The contents held by the latch circuit 12 are supplied to a data bus as pitch data in real time based on the instruction from a processor.
    • 目的:通过将信号的正和负峰值与输入信号的正值和负值进行比较,并且控制触发器,将基频从实时的语音等多个谐波分量的信号中取出。 构成:将声音信号或音乐声音信号通过反向放大器1和2输入到从DC偏置电路6施加了直流电位的峰值检测电路3和4,将直流电位施加到 直流偏置电路5.峰值由电容器C保持。当波形表示峰值时,比较器的输出反相。 SRF / F7设置为正峰值,并在负峰值复位。 SRF / F7的Q输出被输入到微分电路8和延迟电路9.当产生正峰值时,对计时器信号进行计数的计数器11被复位。 紧接在前的值由锁存电路12保持。由锁存电路12保存的内容根据来自处理器的指令实时地作为音调数据提供给数据总线。