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1. 发明申请

WO2011160011A1 ISOLATION BETWEEN NONVOLATILE MEMORY CELLS BY MEANS OF LOW- DIELECTRIC- CONSTANT DIELECTRICS AND AIR GAPS AND CORRESPONDING MANUFACTURING METHOD 审中-公开
标题翻译：通过低介电常数电介质和空气GAPS和相关制造方法的非易失性记忆体之间的分离
公开(公告)号：WO2011160011A1
公开(公告)日：2011-12-22
申请号：PCT/US2011/040874
申请日：2011-06-17
申请人： SANDISK TECHNOLOGIES, INC. , PURAYATH, Vinod, Robert , MATAMIS, George , CHIEN, Henry , KAI, James , ZHANG, Yuan
发明人： PURAYATH, Vinod, Robert , MATAMIS, George , CHIEN, Henry , KAI, James , ZHANG, Yuan
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L21/764
CPC分类号： H01L27/11524 , H01L21/28273 , H01L21/28282 , H01L21/764 , H01L21/7682 , H01L27/11521 , H01L27/11568 , H01L29/0649
摘要： High - density semiconductor memory is provided with enhancements to gate - coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric (438) between control gates (442) and charge storage regions (436) is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Dielectric caps (451,453) are provided between memory cells and have a dielectric constant smaller than the one of the intermediate dielectric (438). Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.
摘要翻译：高密度半导体存储器提供了对非易失性存储器中分立器件之间的栅极耦合和电隔离的增强。控制栅极（442）和电荷存储区域（436）之间的中间电介质（438）在行方向上变化，对于不同的材料，具有不同的介电常数以提供足够的栅极间耦合，同时防止边缘场和寄生电容。绝缘帽（451,453）设置在存储器单元之间并具有小于中间电介质（438）之一的介电常数。至少部分地通过形成在列（位线）方向上的气隙和/或在行（字线）方向上形成的气隙来进一步提供电隔离。

2. 发明申请

WO2012003301A2 ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：超高密度垂直NAND存储器件及其制造方法
公开(公告)号：WO2012003301A2
公开(公告)日：2012-01-05
申请号：PCT/US2011/042566
申请日：2011-06-30
申请人： SANDISK TECHNOLOGIES INC. , ALSMEIER, Johann , PURAYATH, Vinod , CHIEN, Henry , MATAMIS, George , LEE, Yao-Sheng , KAI, James , ZHANG, Yuan , SAMACHISA, George
发明人： ALSMEIER, Johann , PURAYATH, Vinod , CHIEN, Henry , MATAMIS, George , LEE, Yao-Sheng , KAI, James , ZHANG, Yuan , SAMACHISA, George
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/792 , H01L29/788
CPC分类号： H01L29/66833 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/66825 , H01L29/78642 , H01L29/7889 , H01L29/7926
摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.
摘要翻译：单片三维NAND串包括半导体通道，半导体通道的至少一个端部基本上垂直于基板的主表面延伸，多个控制栅电极具有基本上平行于基板的主表面延伸的带状衬底，所述阻挡电介质包括多个阻挡电介质段，多个离散电荷存储段和位于所述多个离散电荷存储段和所述半导体通道中的每一个之间的隧道电介质。

3. 发明申请

WO2011011525A1 METHOD OF FORMING NANOSTRUCTURE-BASED NAND FLASH CELLS AND THE PERIPHERY CIRCUITS THEREOF 审中-公开
标题翻译：形成基于纳米结构的NAND闪存细胞及其周围电路的方法
公开(公告)号：WO2011011525A1
公开(公告)日：2011-01-27
申请号：PCT/US2010/042766
申请日：2010-07-21
申请人： SANDISK CORPORATION , PURAYATH, Vinod, Robert , KAI, James, K. , HIGASHITANI, Masaaki , ORIMOTO, Takashi , MATAMIS, George , CHIEN, Henry
发明人： PURAYATH, Vinod, Robert , KAI, James, K. , HIGASHITANI, Masaaki , ORIMOTO, Takashi , MATAMIS, George , CHIEN, Henry
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115
CPC分类号： H01L21/76224 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/11526 , H01L27/11529 , H01L27/11536 , H01L27/11546 , H01L27/11573 , H01L29/788 , Y10S438/962 , Y10S977/774 , Y10S977/936
摘要： Nanostructure-based charge storage regions (CSR1-CSR5) are included in non-volatile memory devices and integrated with the fabrication of select gates (SGl) and peripheral circuitry (PGl, PG2) One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.
摘要翻译：基于纳米结构的电荷存储区域（CSR1-CSR5）被包括在非易失性存储器件中，并与选择栅极（SG1）和外围电路（PG1，PG2）的制造集成在一个衬底上施加一个或多个纳米结构涂层存储器阵列区域和外围电路区域。提供了用于从衬底的不需要的区域（例如选择栅极和外围晶体管的目标区域）去除纳米结构涂层的各种工艺。在一个实例中，使用基于自组装的工艺来形成一个或多个纳米结构涂层以在衬底的有源区上选择性地形成纳米结构。自组装允许形成彼此电隔离的纳米结构的离散线，而不需要对纳米结构涂层进行图案化或蚀刻。

4. 发明申请

WO2012097153A1 METHOD OF MANUFACTURING AIR GAP ISOLATION IN HIGH-DENSITY NON-VOLATILE MEMORY 审中-公开
标题翻译：在高密度非易失性存储器中制造空气隙分离的方法
公开(公告)号：WO2012097153A1
公开(公告)日：2012-07-19
申请号：PCT/US2012/021081
申请日：2012-01-12
申请人： SANDISK TECHNOLOGIES, INC. , PACHAMUTHU, Jayavel , PURAYATH, Vinod, Robert , MATAMIS, George
发明人： PACHAMUTHU, Jayavel , PURAYATH, Vinod, Robert , MATAMIS, George
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/764
CPC分类号： H01L27/11521 , H01L21/764 , H01L27/11568
摘要： Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Air gaps are formed at least partially in isolation regions between active areas of the substrate. The air gaps may further extend above the substrate surface between adjacent layer stack columns. A sacrificial material is formed at least partially in the isolation regions, followed by forming a dielectric liner. The sacrificial material is removed to define air gaps prior to forming the control gate layer and then etching it and the layer stack columns to form individual control gates and columns of non-volatile storage elements.
摘要翻译：提供了非易失性存储器阵列中的气隙隔离和相关的制造工艺。至少部分地在衬底的有源区域之间的隔离区域中形成气隙。气隙可以在相邻层堆叠柱之间的衬底表面之上进一步延伸。至少部分地在隔离区域中形成牺牲材料，随后形成电介质衬垫。去除牺牲材料以在形成控制栅极层之前限定气隙，然后蚀刻它和层堆叠列以形成单独的控制栅极和列的非易失性存储元件。

5. 发明申请

WO2011160001A1 NON-VOLATILE MEMORY COMPRISING BIT LINE AIR GAPS AND WORD LINE AIR GAPS AND CORRESPONDING MANUFACTURING METHOD 审中-公开
标题翻译：非线性内存包含位线空气和字线空气GAPS和相应的制造方法
公开(公告)号：WO2011160001A1
公开(公告)日：2011-12-22
申请号：PCT/US2011/040859
申请日：2011-06-17
申请人： SANDISK TECHNOLOGIES, INC. , PURAYATH, Vinod, Robert , MATAMIS, George , HARARI, Eli , KINOSHITA, Hiroyuki , PHAM, Tuan
发明人： PURAYATH, Vinod, Robert , MATAMIS, George , HARARI, Eli , KINOSHITA, Hiroyuki , PHAM, Tuan
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/764
CPC分类号： H01L21/764 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps (436) that are elongated in a column direction between the active areas. At least one cap (434) is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps (487) that are elongated in a row direction between adjacent rows of storage elements are also provided. The selective growth processes involve a modification of the surface of the charge storage regions, either by deposition of a catalyst layer or by ion implantation.
摘要翻译：提供了非易失性存储器阵列中的气隙隔离和相关制造工艺。至少部分地可以通过在活动区域之间沿列方向延伸的位线空气间隙（436）来提供衬底的相邻有源区域之间的电隔离。至少一个帽（434）形成在每个隔离区域上，至少部分地覆盖空气以提供相应气隙的上端点。帽可以至少部分地沿着相邻的电荷存储区域的侧壁形成。在各种实施方案中，选择性生长过程用于在隔离区域上形成封盖条以限定气隙。还提供了在相邻行存储元件之间沿行方向延伸的字线气隙（487）。选择性生长方法包括通过沉积催化剂层或通过离子注入来修饰电荷存储区域的表面。

6. 发明申请

WO2011091416A1 DAMASCENE METHOD OF MAKING A NONVOLATILE MEMORY DEVICE 审中-公开
标题翻译：制造非易失性存储器件的DAMASCENE方法
公开(公告)号：WO2011091416A1
公开(公告)日：2011-07-28
申请号：PCT/US2011/022400
申请日：2011-01-25
申请人： SANDISK 3D LLC , PURAYATH, Vinod Robert , MATAMIS, George , KAI, James , ORIMOTO, Takashi
发明人： PURAYATH, Vinod Robert , MATAMIS, George , KAI, James , ORIMOTO, Takashi
IPC分类号： H01L27/10 , H01L27/102
CPC分类号： H01L27/101 , H01L27/1021
摘要： A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.
摘要翻译：一种制造器件的方法包括提供包含由第一绝缘特征分开的第一半导体轨道的第一器件电平，在第一器件电平上形成牺牲层，在第一器件电平图形化牺牲层和第一半导体轨道以形成多个的第二轨道沿着第二方向延伸，其中所述多个第二轨道至少部分地延伸到所述第一装置水平面并且通过至少部分地延伸到所述第一装置水平的轨道形开口彼此分开，所述多个第二轨道，去除所述牺牲层，以及在所述第二设备水平上的第二设备水平的所述第二绝缘特征之间形成第二半导体轨道。第一半导体轨道沿第一方向延伸。第二半导体轨道沿与第一方向不同的第二方向延伸。

7. 发明申请

WO2010059296A1 SELF-ALIGNED THREE-DIMENSIONAL NON-VOLATILE MEMORY FABRICATION 审中-公开
标题翻译：自对准的三维非易失性存储器制造
公开(公告)号：WO2010059296A1
公开(公告)日：2010-05-27
申请号：PCT/US2009/059052
申请日：2009-09-30
申请人： SANDISK 3D LLC , MATAMIS, George , CHIEN, Henry , KAI, James, K. , ORIMOTO, Takashi , PURAYATH, Vinod, R. , PING, Er-Xuan , SCHEUERLEIN, Roy, E.
发明人： MATAMIS, George , CHIEN, Henry , KAI, James, K. , ORIMOTO, Takashi , PURAYATH, Vinod, R. , PING, Er-Xuan , SCHEUERLEIN, Roy, E.
IPC分类号： G11C16/02 , H01L21/822 , H01L27/06 , H01L27/24
CPC分类号： H01L21/20 , G11C13/0004 , G11C17/16 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.
摘要翻译：公开了一种用于三维非易失性存储器的自对准制造工艺。双重蚀刻工艺在与导体下面和上面的记忆柱自对准的给定水平处形成导体。以这种方式形成导体可以包括使用沿给定方向的第一重复图案蚀刻第一导体层以形成导体的第一部分。具有第一图案的蚀刻还限定了下面的柱结构的两个相对的侧壁，从而使导体与支柱自对准。蚀刻后，沉积第二导体层，随后沉积半导体层堆叠。执行以与第一图案相同的方向重复的第二图案的蚀刻，从而形成与上层叠层线自对准的导体的第二部分。然后将这些层堆叠线正交蚀刻以限定覆盖导体的第二组支柱。

8. 发明申请

WO2008088654A1 NAND MEMORY WITH DUAL CONTROL GATES HAVING FIXED CHARGE LAYER BELOW CONTROL GATES 审中-公开
标题翻译：具有双控制门的NAND存储器具有下面的固定充电层下面的控制门
公开(公告)号：WO2008088654A1
公开(公告)日：2008-07-24
申请号：PCT/US2007/088145
申请日：2007-12-19
申请人： SANDISK CORPORATION , CHIEN, Henry , MATAMIS, George , ORIMOTO, Takashi , KAI, James
发明人： CHIEN, Henry , MATAMIS, George , ORIMOTO, Takashi , KAI, James
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/51
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/66825
摘要： A string (200) of nonvolatile memory cells are connected together by source/drain regions (202-205)- that include an inversion layer created by fixed charge in an overlying layer (210-213). Control gates (220-223) extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation. Fixed charges may also be located between floating gates and the underlying substrate surface. Fixed charge over source/drain regions and under floating gates are formed together in a common deposition.
摘要翻译：非易失性存储单元的串（200）由源/漏区（202-205）连接在一起，包括在上层（210-213）中由固定电荷产生的反型层。控制栅极（220-223）在浮动栅极之间延伸，使得两个控制栅极耦合到浮动栅极。可以通过等离子体氮化形成固定电荷层。固定电荷也可以位于浮动栅极和下面的衬底表面之间。源极/漏极区域和浮置栅极之间的固定电荷一起形成在共同的沉积中。

9. 发明申请

WO2011097389A1 NON-VOLATILE MEMORY CELL CONTAINING NANODOTS AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：含有纳米级的非挥发性记忆体及其制备方法
公开(公告)号：WO2011097389A1
公开(公告)日：2011-08-11
申请号：PCT/US2011/023617
申请日：2011-02-03
申请人： SANDISK 3D LLC , KAI, James , CHIEN, Henry , MATAMIS, George
发明人： KAI, James , CHIEN, Henry , MATAMIS, George
IPC分类号： H01L27/24 , H01L45/00 , G11C13/02 , G11C13/00
CPC分类号： B82Y10/00 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C2213/72 , H01L27/2409 , H01L45/04 , H01L45/1233 , H01L45/1273 , H01L45/146 , H01L45/149
摘要： A non-volatile memory cell includes a first electrode (101), a steering element (110), a storage element (118) located in series with the steering element, a plurality of discrete conductive nano - features (211) separated from each other by an insulating matrix (212), where the plurality of discrete nano - features are located in direct contact with the storage element, and a second electrode (100). An alternative non-volatile memory cell includes a plurality of discrete insulating nano - features (211) separated from each other by a conductive matrix (212) instead.
摘要翻译：非易失性存储单元包括与该转向元件串联定位的第一电极（101），转向元件（110），存储元件（118），彼此分离的多个离散的导电纳米特征（211）绝缘基体（212），其中所述多个离散的纳米特征位于与所述存储元件直接接触的位置，以及第二电极（100）。替代的非易失性存储单元包括通过导电矩阵（212）彼此分离的多个分立的绝缘纳米特征（211）。

10. 发明申请

WO2009129053A1 NON-VOLATILE MEMORY WITH SIDEWALL CHANNELS AND RAISED SOURCE/DRAIN REGIONS 审中-公开
标题翻译：非易失性存储器，带有通道和扩展源/漏区
公开(公告)号：WO2009129053A1
公开(公告)日：2009-10-22
申请号：PCT/US2009/039202
申请日：2009-04-01
申请人： SANDISK CORPORATION , CHIEN, Henry , PURAYATH, Vinod, R. , KAI, James , MATAMIS, George , ORIMOTO, Takashi
发明人： CHIEN, Henry , PURAYATH, Vinod, R. , KAI, James , MATAMIS, George , ORIMOTO, Takashi
IPC分类号： G11C11/56 , G11C11/16
CPC分类号： G11C8/10 , G11C8/04 , G11C11/5621 , G11C16/0483 , G11C19/00 , H01L21/28273 , H01L27/11521
摘要： A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.
摘要翻译：一种非易失性存储系统，其中浮动栅极的侧壁绝缘层比底部绝缘层的厚度明显薄，并且其中设置有凸起的源极/漏极区域。在编程或擦除期间，隧道主要通过侧壁绝缘层和凸起的源极/漏极区域而不是通过底部绝缘层发生。浮动门可以具有均匀的宽度或倒T形。凸起的源极/漏极区域可以从衬底外延生长，并且可以包括在未掺杂区域上方的掺杂区域，使得沟道长度从浮置栅极下方有效地延伸并且向上延伸到未掺杂区域，使得短沟道效应为降低。侧壁绝缘层与底部绝缘层的厚度的比可以为约0.3〜0.67。

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