专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2016089467A1 OPERATION MODES FOR AN INVERTED NAND ARCHITECTURE 审中-公开
标题翻译：反向NAND架构的操作模式
公开(公告)号：WO2016089467A1
公开(公告)日：2016-06-09
申请号：PCT/US2015/052071
申请日：2015-09-24
申请人： SANDISK TECHNOLOGIES INC.
发明人： ZHANG, Yanli , SAMACHISA, George , ALSMEIER, Johann , CHEN, Jian
IPC分类号： G11C16/04 , G11C11/56 , G11C16/26
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/10 , G11C16/26
摘要： Methods for performing memory operations on a memory array that includes inverted NAND strings are described. The memory operations may include erase operations, read operations, programming operations, program verify operations, and erase verify operations. An inverted NAND string may include a string of inverted floating gate transistors or a string of inverted charge trap transistors. In one embodiment, an inverted floating gate transistor may include a tunneling layer between a floating gate of the inverted floating gate transistor and a control gate of the inverted floating gate transistor. The arrangement of the tunneling layer between the floating gate and the control gate allows electrons to be added to or removed from the floating gate via F-N tunneling between the floating gate and the control gate. The inverted NAND string may be formed above a substrate and oriented such that the inverted NAND string is orthogonal to the substrate.
摘要翻译：描述了对包括反相NAND串的存储器阵列执行存储器操作的方法。存储器操作可以包括擦除操作，读取操作，编程操作，程序验证操作和擦除验证操作。反相NAND串可以包括一串反向浮栅晶体管或一串反向电荷陷阱晶体管。在一个实施例中，反相浮栅晶体管可以包括在反相浮栅晶体管的浮置栅极和反相浮栅晶体管的控制栅极之间的隧穿层。浮动栅极和控制栅极之间的隧道层的布置允许通过浮动栅极和控制栅极之间的F-N隧穿将电子添加到浮动栅极或从浮动栅极去除。反相NAND串可以形成在衬底之上并且被定向成使得反相NAND串与衬底正交。

2. 发明申请

WO2016053453A1 3D SEMICIRCULAR VERTICAL NAND STRING WITH SELF ALIGNED FLOATING GATE OR CHARGE TRAP CELL MEMORY CELLS AND METHODS OF FABRICATING AND OPERATING THE SAME 审中-公开
标题翻译：具有自对准浮动门或充电陷阱细胞存储器电池的3D半圆形垂直NAND晶体及其制造和操作方法
公开(公告)号：WO2016053453A1
公开(公告)日：2016-04-07
申请号：PCT/US2015/042220
申请日：2015-07-27
申请人： SANDISK TECHNOLOGIES INC.
发明人： KAI, James K. , ZHANG, Yanli , CHIEN, Henry , ALSMEIER, Johann , SEROV, Andrey
IPC分类号： H01L27/115
CPC分类号： H01L27/11556 , G11C16/0408 , G11C16/0483 , G11C16/14 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/66666 , H01L29/66825 , H01L29/7827
摘要： A memory device includes a plurality of memory cells arranged in a string substantially perpendicular to the major surface of the substrate (10) in a plurality of device levels, at least one first select gate electrode located between the major surface of the substrate and the plurality of memory cells, at least one second select gate electrode located above the plurality of memory cells, a semiconductor channel (601) having a portion that extends vertically along a direction perpendicular to the major surface, a first memory film (54) contacting a first side of the semiconductor channel, and a second memory film (54) contacting a second side of the semiconductor channel. The second memory film is electrically isolated from the first memory film, and is located at a same level as the first memory film.
摘要翻译：存储器件包括多个存储单元，多个存储单元以多个器件级别布置成基本上垂直于衬底（10）的主表面的串，至少一个第一选择栅极位于衬底的主表面和多个器件级之间存储单元的至少一个第二选择栅极，位于所述多个存储单元上方的至少一个第二选择栅电极，具有沿垂直于所述主表面的方向垂直延伸的部分的半导体沟道（601），与第一存储单元接触的第一存储膜半导体通道的第二侧和与半导体通道的第二侧接触的第二存储膜（54）。第二存储膜与第一存储膜电隔离，并且位于与第一存储膜相同的水平。

3. 发明申请

WO2016028621A1 FLOATING GATE ULTRAHIGH DENSITY VERTICAL NAND FLASH MEMORY AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：浮动门超高密度垂直NAND闪存及其制作方法
公开(公告)号：WO2016028621A1
公开(公告)日：2016-02-25
申请号：PCT/US2015/045205
申请日：2015-08-14
申请人： SANDISK TECHNOLOGIES INC.
发明人： MAKALA, Raghuveer , ZHANG, Yanli , LEE, Yao-Sheng , KANAKAMEDALA, Senaka , SHARANGPANI, Rahul , MATAMIS, George , ALSMEIER, Johann , SHIMABUKURO, Seiji , MIZUNO, Genta , TAKEGUCHI, Naoki
IPC分类号： H01L27/115
CPC分类号： H01L27/11556 , H01L27/11582
摘要： A method of making a monolithic three dimensional NAND string including providing a stack of alternating first material layers and second material layers over a substrate. The first material layers comprise an insulating material and the second material layers comprise sacrificial layers. The method also includes forming a back side opening in the stack, selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers and forming a blocking dielectric (7) inside the back side recesses and the back side opening. The blocking dielectric (7) has a clam shaped regions inside the back side recesses. The method also includes forming a plurality of copper control gate electrodes (3) in the respective clam shell shaped regions of the blocking dielectric in the back side recesses.
摘要翻译：一种制造单片三维NAND串的方法，包括在衬底上提供交替的第一材料层和第二材料层的堆叠。第一材料层包括绝缘材料，第二材料层包括牺牲层。该方法还包括在堆叠中形成背侧开口，通过后侧开口选择性地去除第二材料层，以在相邻的第一材料层之间形成背侧凹槽，并在背侧凹槽和背面之间形成阻挡电介质（7）侧面开口。阻挡电介质（7）在背侧凹部内部具有蛤状区域。该方法还包括在后侧凹部中在阻挡电介质的相应蛤壳形区域中形成多个铜控制栅电极（3）。

4. 发明申请

WO2016064530A1 NAND MEMORY STRINGS AND METHODS OF FABRICATION THEREOF 审中-公开
标题翻译： NAND存储器及其制造方法
公开(公告)号：WO2016064530A1
公开(公告)日：2016-04-28
申请号：PCT/US2015/052191
申请日：2015-09-25
申请人： SANDISK TECHNOLOGIES, INC.
发明人： KOKA, Sateesh , MAKALA, Raghuveer , ZHANG, Yanli , KANAKAMEDALA, Senaka , SHARANGPANI, Rahul , LEE, Yao-Sheng , MATAMIS, George
IPC分类号： H01L27/115 , H01L29/792 , H01L29/788 , H01L29/66
CPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/66666 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different etching process to remove a damaged portion of the semiconductor substrate from the bottom of the memory opening. A single crystal semiconductor material is formed over the substrate in the memory opening using an epitaxial growth process. Additional embodiments include improving the quality of the interface between the semiconductor channel material and the underlying semiconductor layers in the memory opening which may be damaged by the bottom opening etch, including forming single crystal semiconductor channel material by epitaxial growth from the bottom surface of the memory opening and/or oxidizing surfaces exposed to the bottom opening etch and removing the oxidized surfaces prior to forming the channel material. Monolithic three-dimensional memory devices formed by the embodiment methods are also disclosed.
摘要翻译：制造单片三维存储器件的方法包括执行第一蚀刻以形成存储器开口和使用不同蚀刻工艺的第二蚀刻，以从存储器开口的底部去除半导体衬底的损坏部分。使用外延生长工艺在存储器开口中的衬底上形成单晶半导体材料。另外的实施例包括提高存储器开口中的半导体沟道材料和底层半导体层之间的界面的质量，这可能被底部开口蚀刻损坏，包括通过从存储器的底表面进行外延生长形成单晶半导体沟道材料暴露于底部开口蚀刻的开口和/或氧化表面，并在形成沟道材料之前去除氧化的表面。还公开了通过实施方式形成的单片三维存储器件。

5. 发明申请

WO2016043968A1 THREE DIMENSIONAL NAND DEVICE HAVING NONLINEAR CONTROL GATE ELECTRODES AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：具有非线性控制栅电极的三维NAND器件及其制造方法
公开(公告)号：WO2016043968A1
公开(公告)日：2016-03-24
申请号：PCT/US2015/047932
申请日：2015-09-01
申请人： SANDISK TECHNOLOGIES INC.
发明人： ZHANG, Yanli , ALSMEIER, Johann
IPC分类号： H01L27/115 , H01L29/792 , H01L29/788 , H01L29/66
CPC分类号： H01L27/11582 , G11C16/0483 , G11C16/06 , H01L21/02365 , H01L21/28273 , H01L21/28282 , H01L21/283 , H01L21/31 , H01L21/32133 , H01L21/768 , H01L21/823412 , H01L21/823418 , H01L21/823468 , H01L21/823475 , H01L21/823487 , H01L23/528 , H01L27/11519 , H01L27/11521 , H01L27/11556 , H01L27/11565 , H01L27/11568 , H01L29/0657 , H01L29/41775 , H01L29/42328 , H01L29/42336 , H01L29/42344 , H01L29/42352 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate in at least one active region, a plurality of semiconductor channels having at least one end portion of each of the plurality of semiconductor channels extending substantially perpendicular to the major surface of the substrate, at least one memory film located between each of the plurality of control gate electrodes and each respective semiconductor channel of the plurality of semiconductor channels, and at least one first slit trench extending substantially perpendicular to the major surface of the substrate. Each of the plurality of control gate electrodes has a nonlinear side wall adjacent to the at least one first slit trench in the at least one active region.
摘要翻译：单片三维NAND串包括在至少一个有源区域中基本上平行于衬底的主表面延伸的多个控制栅电极，多个半导体沟道具有多个半导体沟道中的每一个的至少一个端部延伸基本上垂直于衬底的主表面，位于多个控制栅电极中的每一个和多个半导体沟道中的每个相应半导体沟道之间的至少一个存储膜，以及至少一个基本上垂直于主体的第一狭缝沟槽基板的表面。多个控制栅极电极中的每一个具有与至少一个有源区域中的至少一个第一狭缝沟槽相邻的非线性侧壁。

6. 发明申请

WO2015200021A1 THREE DIMENSIONAL NAND DEVICE WITH CHANNEL CONTACTING CONDUCTIVE SOURCE LINE AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：具有通道接触导通线的三维NAND器件及其制造方法
公开(公告)号：WO2015200021A1
公开(公告)日：2015-12-30
申请号：PCT/US2015/035779
申请日：2015-06-15
申请人： SANDISK TECHNOLOGIES INC.
发明人： ZHANG, Yanli , SHOJI, Go , ALSMEIER, Johann , PACHAMUTHU, Jayavel , DONG, Yingda , YUAN, Jiahui
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/11529 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/7883
摘要： A NAND memory cell region of a NAND device includes a conductive source line that extends substantially parallel to a major surface of a substrate, a first semiconductor channel that extends substantially perpendicular to a major surface of the substrate, and a second semiconductor channel that extends substantially perpendicular to the major surface of the substrate. At least one of a bottom portion and a side portion of the first semiconductor channel contacts the conductive source line and at least one of a bottom portion and a side portion of the second semiconductor channel contacts the conductive source line.
摘要翻译： NAND器件的NAND存储器单元区域包括基本上平行于衬底的主表面延伸的导电源线，基本上垂直于衬底的主表面延伸的第一半导体沟道，以及基本上延伸垂直于基片的主表面。第一半导体沟道的底部和侧部中的至少一个与导电源线接触，并且第二半导体沟道的底部和侧部中的至少一个与导电源线接触。

7. 发明申请

WO2013141968A1 COMPACT THREE DIMENSIONAL VERTICAL NAND AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：紧凑的三维垂直NAND及其制作方法
公开(公告)号：WO2013141968A1
公开(公告)日：2013-09-26
申请号：PCT/US2013/024638
申请日：2013-02-04
申请人： SANDISK TECHNOLOGIES, INC.
发明人： ALSMEIER, Johann , MAKALA, Raghuveer S. , COSTA, Xiying , ZHANG, Yanli
IPC分类号： H01L29/788 , H01L21/764 , H01L29/792 , H01L27/115 , G11C16/04 , H01L29/66
CPC分类号： H01L27/11551 , G11C16/04 , G11C16/0483 , H01L21/764 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/66666 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7889 , H01L29/7926
摘要： A NAND device has at least a 3x3 sub-array of vertical NAND strings (180) in which the control gate electrodes (3, 3a, 3b, 3aL, 3aR) are continuous in the sub-array and do not have an air gap or a dielectric filled trench in the sub-array. An air gap or a dielectric filled trench (53, 63) separates a lower (51) respectively upper (61) select gate of the NAND from the corresponding select gates of neighbouring NAND strings in the same sub-array. An air gap or a dielectric filled trench (81) can separate different sub-array blocks of the whole array of NAND strings. The NAND device is formed by first forming a lower select gate level (50) having separated lower select gates (51), then forming plural memory device levels containing a plurality of NAND string portions comprising continuous, mesh-shaped control gate electrodes (3), and then forming an upper select gate level (60) over the memory device levels having separated upper select gates (61).
摘要翻译： NAND器件至少具有垂直NAND串（180）的3×3子阵列，其中控制栅电极（3,3a，3b，3aL，3aR）在子阵列中是连续的并且不具有气隙或子阵列中的介电填充沟槽。气隙或介质填充沟槽（53,63）将NAND的下（51）分别上（61）选择栅极与相同子阵列中的相邻NAND串的对应选择栅极分离。气隙或电介质填充沟槽（81）可以分离整个NAND串阵列的不同子阵列块。 NAND器件通过首先形成具有分离的下选择栅极（51）的下选择栅极电平（50）形成，然后形成包含多个NAND串部分的多个存储器件级，该多个NAND串部分包括连续的网状控制栅电极（3），然后在具有分离的上选择栅极（61）的存储器件级上形成上选择栅极电平（60）。

8. 发明申请

WO2016032838A2 MONOLITHIC THREE DIMENSIONAL NAND STRINGS AND METHODS OF FABRICATION THEREOF 审中-公开
标题翻译：单片三维NAND条及其制作方法
公开(公告)号：WO2016032838A2
公开(公告)日：2016-03-03
申请号：PCT/US2015/046035
申请日：2015-08-20
申请人： SANDISK TECHNOLOGIES INC.
发明人： MAKALA, Raghuveer S. , ZHANG, Yanli , SHARANGPANI, Rahul , LEE, Yao-Sheng , KANAKAMEDALA, Senaka Krishna , MATAMIS, George , ALSMEIER, Johann
IPC分类号： H01L27/115
CPC分类号： H01L29/66825 , H01L21/7682 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/66833
摘要： Methods of making a monolithic three dimensional NAND string that include forming a stack of alternating first material layers and second material layers over a substrate, where each of the second material layers includes a layer of a first silicon oxide material between two layers of a second silicon oxide material different from the first silicon oxide material, etching the stack to form a front side opening in the stack, forming a memory film over a sidewall of the front side opening, and forming a semiconductor channel in the front side opening such that at least a portion of the memory film is located between the semiconductor channel and the sidewall of the front side opening, where at least one of an air gap or a material which has a dielectric constant below 3.9 is formed between the respective two layers of second silicon oxide material.
摘要翻译：制造单片三维NAND串的方法包括在衬底上形成交替的第一材料层和第二材料层的堆叠，其中每个第二材料层包括在第二硅层的两层之间的第一氧化硅材料层氧化物材料，不同于第一氧化硅材料，蚀刻堆叠以在堆叠中形成前侧开口，在前侧开口的侧壁上形成记忆膜，并且在前侧开口中形成半导体通道，使得至少存储膜的一部分位于半导体通道和前侧开口的侧壁之间，其中在相应的两层第二氧化硅之间形成气隙或介电常数低于3.9的材料中的至少一个材料。

9. 发明申请

WO2016028466A1 THREE DIMENSIONAL NAND DEVICE HAVING DUMMY MEMORY HOLES AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：具有二维记忆孔的三维NAND器件及其制造方法
公开(公告)号：WO2016028466A1
公开(公告)日：2016-02-25
申请号：PCT/US2015/043096
申请日：2015-07-31
申请人： SANDISK TECHNOLOGIES INC.
发明人： ZHANG, Yanli , MAKALA, Raghuveer S. , ALSMEIER, Johann , LEE, Yao-Sheng , XU, Tiger
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L21/02532 , H01L21/31111 , H01L21/32133 , H01L27/11548 , H01L27/11556 , H01L27/11575 , H01L27/11578 , H01L29/16 , H01L29/495 , H01L29/7845 , H01L29/7883 , H01L29/7926
摘要： A monolithic three dimensional NAND string includes a plurality of control gate electrodes (3a, b) extending substantially parallel to a major surface of a substrate (100), a memory opening (150) extending substantially perpendicular to the major surface of the substrate and filled with a memory opening material including a memory film (7, 9, 11), and a dummy opening (160) extending substantially perpendicular to the major surface of the substrate and filled with a dummy channel material which is different from the memory opening material. The dummy channel material has a higher Young's modulus than the memory opening material to offset warpage of the substrate due to the one of compressive and tensile stress imposed by the plurality of control gate electrodes on the substrate.
摘要翻译：单片三维NAND串包括基本上平行于基板（100）的主表面延伸的多个控制栅电极（3a，b），基本上垂直于基板主表面延伸的存储器开口（150）具有包括记忆膜（7,9,11）的存储器开口材料和基本上垂直于衬底的主表面延伸的虚拟开口（160），并且填充有与存储器开口材料不同的虚拟通道材料。虚拟通道材料具有比存储器开口材料更高的杨氏模量，以抵消由于基板上的多个控制栅电极施加的压缩和拉伸应力之一而导致的基板翘曲。

10. 发明申请

WO2016003638A1 METHODS OF MAKING THREE DIMENSIONAL NAND DEVICES 审中-公开
标题翻译：制造三维NAND器件的方法
公开(公告)号：WO2016003638A1
公开(公告)日：2016-01-07
申请号：PCT/US2015/035961
申请日：2015-06-16
申请人： SANDISK TECHNOLOGIES INC.
发明人： MAKALA, Raghuveer S. , LEE, Yao-Sheng , KANAKAMEDALA, Senaka Krishna , ZHANG, Yanli , MATAMIS, George , ALSMEIER, Johann
IPC分类号： H01L27/115 , H01L29/423
CPC分类号： H01L27/11556 , H01L21/02123 , H01L21/02164 , H01L21/0217 , H01L21/02186 , H01L21/28273 , H01L21/28556 , H01L21/28568 , H01L27/11519 , H01L27/11524 , H01L27/11526 , H01L29/42324 , H01L29/495 , H01L29/511 , H01L29/518 , H01L29/7827
摘要： A method of making a three dimensional NAND string includes providing a stack of alternating first material layers and second material layers over a substrate. The method further includes forming a front opening in the stack, forming a tunnel dielectric in the front side opening, forming a semiconductor channel in the front side opening over the tunnel dielectric and forming a back side opening in the stack. The method also includes selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers, forming a metal charge storage layer in the back side opening and in the back side recesses and forming discrete charge storage regions in the back side recesses by removing the metal charge storage layer from the back side opening and selectively recessing the metal charge storage layer in the back side recesses.
摘要翻译：制造三维NAND串的方法包括在衬底上提供交替的第一材料层和第二材料层的堆叠。所述方法还包括在所述堆叠中形成前开口，在所述前侧开口中形成隧道电介质，在所述隧道电介质的前侧开口中形成半导体沟道，并在所述堆叠中形成背面开口。该方法还包括通过后侧开口选择性地去除第二材料层，以在相邻的第一材料层之间形成背侧凹槽，在后侧开口和后侧凹槽中形成金属电荷存储层，并在后侧凹槽中形成离散电荷存储区域通过从后侧开口去除金属电荷存储层并选择性地使金属电荷存储层在后侧凹部中凹陷来使背面凹陷。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式