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1. 发明申请

WO2016022319A2 PROTECTIVE MATERIAL TO PREVENT SHORT CIRCUITS IN THREE-DIMENSIONAL MEMORY DEVICE 审中-公开
标题翻译：防止三维存储设备中的短路的保护材料
公开(公告)号：WO2016022319A2
公开(公告)日：2016-02-11
申请号：PCT/US2015/042302
申请日：2015-07-27
申请人： SANDISK TECHNOLOGIES INC.
发明人： YUAN, Jiahui , PACHAMUTHU, Jayavel , DONG, Yingda , ZHAO, Wei
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , G01R31/025 , G11C16/0483 , G11C29/025 , H01L21/32136 , H01L21/76224 , H01L27/0255 , H01L27/0288 , H01L27/0629 , H01L27/11519 , H01L27/11524 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L28/20 , H01L28/40 , H01L29/16 , H01L29/42328 , H01L29/42344 , H01L29/6609 , H01L29/861
摘要： In a three-dimensional stacked non-volatile memory device, a short circuit is prevented in a select gate layer by providing a protective material such as a diode, capacitor, linear resistor or varistor between select gate lines and a remaining portion of the select gate layer. Charges which are accumulated in the select gate lines due to plasma etching are therefore prevented from discharging through the remaining portion in a short circuit path when the select gate lines are driven. The protective material can comprise a p-n diode, an n-i-n or p-i-p resistor, a thin oxide layer between doped polysilicon layers in a capacitor, or a variable-resistance material such as ZnO2 between oxide layers in a varistor.
摘要翻译：在三维堆叠式非易失性存储器件中，通过在选择栅极线之间提供诸如二极管，电容器，线性电阻器或变阻器之类的保护材料来防止选择栅极层中的短路和选择栅极层的剩余部分。因此，当选择栅极线被驱动时，由于等离子体蚀刻而累积在选择栅极线中的电荷被阻止通过短路路径中的剩余部分放电。保护材料可以包括p-n二极管，n-i-n或p-i-p电阻器，电容器中掺杂多晶硅层之间的薄氧化物层，或变阻器中氧化物层之间的可变电阻材料，例如ZnO2。

2. 发明申请

WO2016053544A1 MODIFYING PROGRAM PULSES BASED ON INTER-PULSE PERIOD TO REDUCE PROGRAM NOISE 审中-公开
标题翻译：基于脉冲周期修改程序脉冲以减少程序噪声
公开(公告)号：WO2016053544A1
公开(公告)日：2016-04-07
申请号：PCT/US2015/047808
申请日：2015-08-31
申请人： SANDISK TECHNOLOGIES INC.
发明人： DONG, Yingda , PANG, Liang , YUAN, Jiahui
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0466 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： Techniques are provided for more accurately programming memory cells by reducing program noise caused by charge loss in a programming pass in which the number of verify tests varies in different program loops. In an nth program loop, at least one programming characteristic is modified based on the number (N) of data states which were subject to verify tests in the n-1st program loop. For example, a reduced step size or pulse duration, or an elevated bit line voltage (Vbl) can be used. The reduction in the step size or pulse duration, or the increase in Vbl, is proportional to N. The modification of the at least one programming characteristic results in a slowdown of the programming of the memory cells so that program noise is reduced.
摘要翻译：提供了通过减少在不同程序循环中验证测试数量变化的编程通过中的电荷损失引起的程序噪声来提供更精确地编程存储器单元的技术。在第n个程序循环中，基于在第n-1程序循环中进行验证测试的数据状态数（N）来修改至少一个编程特性。例如，可以使用减小的步长或脉冲持续时间，或升高的位线电压（Vbl）。步长或脉冲持续时间的减小或Vbl的增加与N成比例。至少一个编程特性的修改导致存储器单元的编程减慢，从而减少编程噪声。

3. 发明申请

WO2016057202A1 PROGRAMMING OF DRAIN SIDE WORD LINE TO REDUCE PROGRAM DISTURB AND CHARGE LOSS 审中-公开
标题翻译：排水侧边线编程减少程序干扰和充电损失
公开(公告)号：WO2016057202A1
公开(公告)日：2016-04-14
申请号：PCT/US2015/051275
申请日：2015-09-21
申请人： SANDISK TECHNOLOGIES INC.
发明人： YUAN, Jiahui , DONG, Yingda , LU, Ching-Huang , ZHAO, Wei
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/3427 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
摘要： Techniques are provided for programming the memory cells of a drain-side edge word line of a set of word lines before programming memory cells of any other word line of the set. Pass voltages applied to the other word lines act as stress pulses which redistribute holes in the charge-trapping material of the memory cells of the other word lines to reduce short-term charge loss and downshifting of the threshold voltage. Additionally, one or more initial program voltages used for the drain-side edge word line are relatively low and also act as stress pulses. The memory cells of the drain-side edge word line are programmed to a narrower Vth window than the memory cells of the other word lines. This compensates for a higher level of program disturb of erased state memory cells of the drain-side edge word line due to reduced channel boosting.
摘要翻译：提供了在编程集合的任何其他字线的存储器单元之前对一组字线集合的漏极边缘字线的存储器单元进行编程的技术。施加到其它字线的通过电压作为应力脉冲，其重新分配其它字线的存储单元的电荷捕获材料中的空穴，以减少阈值电压的短期电荷损耗和降档。此外，用于漏极侧边缘字线的一个或多个初始编程电压相对较低并且还用作应力脉冲。漏极侧边缘字线的存储单元被编程到比其它字线的存储单元窄的Vth窗口。这由于减少的信道增强而补偿了漏极侧边缘字线的擦除状态存储单元的编程干扰的较高水平。

4. 发明公开

EP2718934A1 INTELLIGENT SHIFTING OF READ PASS VOLTAGES FOR NON-VOLATILE STORAGE 有权转让
标题翻译：阅读THROUGH紧张关系非易失性存储器的智能型交换
公开(公告)号：EP2718934A1
公开(公告)日：2014-04-16
申请号：EP12726555.1
申请日：2012-05-31
申请人： SanDisk Technologies Inc.
发明人： YUAN, Jiahui , DONG, Yingda , KWONG, Charles
IPC分类号： G11C11/56 , G11C16/34 , G11C16/26
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3454 , G11C16/349 , G11C29/021 , G11C29/028
摘要： A first read pass voltage is determined and optimized for cycled memory. One or more starting read pass voltages are determined for one or more dies. The system dynamically calculates a current read pass voltage based on the number of program/erase erase cycles, the first read pass voltage and the respective starting read pass voltage. Data is read from one or more non-volatile storage elements using the calculated current read pass voltage.

5. 发明申请

WO2016022320A1 BIAS TO DETECT AND PREVENT SHORT CIRCUITS IN THREE-DIMENSIONAL MEMORY DEVICE 审中-公开
标题翻译：检测和预防三维存储器件中的短路电路
公开(公告)号：WO2016022320A1
公开(公告)日：2016-02-11
申请号：PCT/US2015/042305
申请日：2015-07-27
申请人： SANDISK TECHNOLOGIES INC.
发明人： YUAN, Jiahui , PACHAMUTHU, Jayavel , DONG, Yingda , ZHAO, Wei
IPC分类号： G11C16/24 , G11C29/02
CPC分类号： G11C16/10 , G11C7/12 , G11C16/24 , G11C16/26 , G11C29/021 , G11C29/025 , G11C29/028 , G11C2029/1204 , G11C2213/71 , H01L21/8221
摘要： In a three-dimensional stacked non-volatile memory device, a short circuit in a select gate layer is detected and prevented. A short circuit occurs when charges accumulated in select gate lines due to plasma etching, discharge through a the select gate layer in a short circuit path when the select gate lines are driven. To detect a short circuit, during a testing phase, an increasing bias is applied to the remaining portion while a current is measured. An increase in the current above a threshold indicates the bias exceeds a breakdown voltage of a short circuit path. A value of the bias at this time is recorded as an optimal bias. During subsequent operations involving select gate transistors or memory cells, such as programming, erasing or reading, the optimal bias is applied when the select gate lines are driven to prevent a current flow through the short circuit.
摘要翻译：在三维堆叠式非易失性存储器件中，检测并防止了选择栅极层中的短路。当选择栅极线由于等离子体蚀刻而累积的电荷在选择栅极线被驱动时通过选择栅极层在短路路径中放电而发生短路。为了检测短路，在测试阶段期间，当测量电流时，向剩余部分施加增加的偏差。高于阈值的电流增加表示偏压超过短路路径的击穿电压。此时的偏差值被记录为最佳偏差。在涉及选择栅晶体管或存储单元（例如编程，擦除或读取）的后续操作期间，当驱动选择栅极线以防止电流流过短路时施加最佳偏压。

6. 发明申请

WO2016003770A1 LOOK AHEAD READ METHOD FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：查看非易失性存储器的前瞻性读取方法
公开(公告)号：WO2016003770A1
公开(公告)日：2016-01-07
申请号：PCT/US2015/037805
申请日：2015-06-25
申请人： SANDISK TECHNOLOGIES INC.
发明人： YUAN, Jiahui , DONG, Yingda , ZHAO, Wei
IPC分类号： G11C11/56 , G11C16/26 , G11C16/34 , H01L27/115
CPC分类号： G11C16/34 , G11C11/5642 , G11C16/26 , G11C16/3427 , G11C2211/5648 , H01L27/1157 , H01L27/11582
摘要： A read operation for selected memory cell on a selected word line compensates for program disturb which is a nonlinear function of the data state of an adjacent memory cell on an adjacent word line. When a command to perform a read operation for the selected memory cell is received, a read operation is first performed on the adjacent memory cell to determine its data state, or to classify the adjacent memory cell into a threshold voltage range which includes one or more data states, or a portion of a data state. The selected memory cell is then read using a baseline control gate voltage which does not provide compensation, and one or more elevated control gate voltages which provide compensation, to distinguish between two adjacent data states. An optimal sensing result is selected based on the data state or threshold voltage range of the adjacent memory cell.
摘要翻译：对所选择的字线上的所选存储单元的读操作补偿作为相邻字线上相邻存储单元的数据状态的非线性函数的程序干扰。当接收到对所选择的存储单元执行读取操作的命令时，首先对相邻的存储器单元执行读取操作以确定其数据状态，或将相邻的存储器单元分类为包括一个或多个数据状态或数据状态的一部分。然后使用不提供补偿的基线控制栅极电压以及提供补偿的一个或多个升高的控制栅极电压来读取所选择的存储器单元，以区分两个相邻的数据状态。基于相邻存储单元的数据状态或阈值电压范围来选择最佳感测结果。

7. 发明申请

WO2015164050A1 NEIGHBORING WORD LINE PROGRAM DISTURB COUNTERMEASURE FOR CHARGE-TRAPPING STACKED MEMORY 审中-公开
标题翻译：邻接字线程序用于收集堆叠存储器的距离计数器
公开(公告)号：WO2015164050A1
公开(公告)日：2015-10-29
申请号：PCT/US2015/024273
申请日：2015-04-03
申请人： SANDISK TECHNOLOGIES INC.
发明人： YUAN, Jiahui , DONG, Yingda , CHEN, Jian
IPC分类号： G11C11/56 , G11C16/26 , G11C16/34 , H01L27/115
CPC分类号： G06F11/1004 , G11C11/5642 , G11C16/0466 , G11C16/10 , G11C16/26 , G11C16/3427 , H01L27/11582
摘要： Techniques are provided for reading data from memory cells arranged along a common charge trapping layer, e.g., in a 3D stacked non-volatile memory device. Memory cells on a word line layer WLLn are disturbed by programming of memory cells on an adjacent word line layer WLLn+1, resulting in uncorrectable errors. The memory cells on WLLn can be read in a data recovery read operation which applies an elevated pass voltage to WLLn+1. The elevated pass voltage causes a decrease and narrowing of the threshold voltage distribution on WLLn which facilitates reading. The operation compensates for the lower threshold voltages by lowering the control gate voltage, raising the source voltage or adjusting a sensing period, demarcation level or pre-charge level in sensing circuitry. The elevated pass voltage can be stepped up in repeated read attempts until there are no uncorrectable errors or a limit is reached.
摘要翻译：提供了用于从沿着公共电荷捕获层布置的存储器单元读取数据的技术，例如在3D堆叠的非易失性存储器件中。字线层WLLn上的存储单元被相邻字线层WLLn + 1上的存储单元的编程所扰乱，导致不可校正的错误。 WLLn上的存储单元可以在数据恢复读取操作中读取，该操作将提升的通过电压施加到WLLn + 1。升高的通过电压导致WLLn上的阈值电压分布的减小和变窄，这有利于读取。该操作通过降低控制栅极电压，提高电源电压或调整感测电路中的感测周期，分界电平或预充电电平来补偿较低的阈值电压。升高的通过电压可以在重复的读取尝试中加强，直到没有不可校正的错误或达到极限。

8. 发明申请

WO2012170282A1 INTELLIGENT SHIFTING OF READ PASS VOLTAGES FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：非易失性存储器的读取电压的智能转换
公开(公告)号：WO2012170282A1
公开(公告)日：2012-12-13
申请号：PCT/US2012/040311
申请日：2012-05-31
申请人： SANDISK TECHNOLOGIES, INC. , YUAN, Jiahui , DONG, Yingda , KWONG, Charles
发明人： YUAN, Jiahui , DONG, Yingda , KWONG, Charles
IPC分类号： G11C11/56 , G11C16/34 , G11C16/26
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3454 , G11C16/349 , G11C29/021 , G11C29/028
摘要： A first read pass voltage is determined and optimized for cycled memory. One or more starting read pass voltages are determined for one or more dies. The system dynamically calculates a current read pass voltage based on the number of program/erase erase cycles, the first read pass voltage and the respective starting read pass voltage. Data is read from one or more non-volatile storage elements using the calculated current read pass voltage.
摘要翻译：确定并优化循环存储器的第一个读通过电压。为一个或多个管芯确定一个或多个启动读通过电压。该系统基于编程/擦除擦除周期的数量，第一读取通过电压和相应的启动读取通过电压来动态地计算当前的读取通过电压。使用计算出的电流读通过电压从一个或多个非易失性存储元件读取数据。

9. 发明申请

WO2016053558A1 READ WITH LOOK-BACK COMBINED WITH PROGRAMMING WITH ASYMMETRIC BOOSTING IN MEMORY 审中-公开
标题翻译：阅读与后退组合与内存中的不对称增强编程
公开(公告)号：WO2016053558A1
公开(公告)日：2016-04-07
申请号：PCT/US2015/048001
申请日：2015-09-01
申请人： SANDISK TECHNOLOGIES INC.
发明人： YUAN, Jiahui , DONG, Yingda , KWONG, Charles , CHEN, Hong-Yan , PANG, Liang
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G11C16/3427 , G06F11/1068 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/3459 , G11C29/52
摘要： A read operation compensates for program disturb when distinguishing between an erased-state and a lowest programmed data state, where the program disturb is a function of the data state of an adjacent, previously-programmed memory cell on a common charge-trapping layer. The read operation occurs in connection with a programming operation which avoids program disturb of the programmed data states by using asymmetric pass voltages. Before reading memory cells on a selected word line, WLn, memory cells on WLn-1 are read. The read operation for WLn uses multiple read voltages - one for each data state on WLn-1, and one of the read results is selected based on the data state of the adjacent memory cell. Other read operations distinguish between each pair of adjacent programmed data states using a read voltage which is independent of the data state of the adjacent memory cell.
摘要翻译：当识别擦除状态和最低编程数据状态时，读取操作补偿程序干扰，其中程序干扰是公共电荷俘获层上相邻的预先编程的存储器单元的数据状态的函数。读操作与编程操作相关，通过使用不对称通过电压避免编程数据状态的程序干扰。在读取所选字线上的存储单元之前，WLn读取WLn-1上的存储单元。 WLn的读取操作使用多个读取电压 - 一个用于WLn-1上的每个数据状态，并且根据相邻存储器单元的数据状态选择一个读取结果。其他读取操作使用独立于相邻存储器单元的数据状态的读取电压来区分每对相邻的编程数据状态。

10. 发明申请

WO2016032705A1 CHARGE REDISTRIBUTION DURING ERASE IN CHARGE TRAPPING MEMORY 审中-公开
标题翻译：电荷捕捉存储器中的擦除期间的充电重新分配
公开(公告)号：WO2016032705A1
公开(公告)日：2016-03-03
申请号：PCT/US2015/043726
申请日：2015-08-05
申请人： SANDISK TECHNOLOGIES INC.
发明人： YUAN, Jiahui , LU, Ching-Huang , DONG, Yingda
IPC分类号： G11C11/56 , G11C16/04 , G11C16/16 , G11C16/34 , H01L27/115
CPC分类号： G11C16/14 , G11C11/5635 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/16 , G11C16/26 , G11C16/3418 , G11C16/344 , G11C16/3445 , G11C2211/5621 , H01L27/11582
摘要： Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after programming. As a result, short-term charge loss after programming is reduced. In one aspect, a positive control gate voltage is applied to a set of memory cells after erase and before programming. The positive control gate voltage has a relatively low amplitude and a long duration, compared to a programming voltage. The positive control gate voltage can be adjusted based on the erase depth of the memory cells and factors such as a count of program-erase cycles, a count of erase-verify iterations, sensing of a position of the lower tail, and a cross-sectional width of a vertical pillar of a memory hole.
摘要翻译：提供了技术来加速与擦除操作相关的孔的再分配，使得在编程之后孔将再次分配。因此，编程后的短期电荷损失减少。在一个方面，在擦除和编程之前，将一个正的控制栅极电压施加到一组存储器单元。与编程电压相比，正控制栅极电压具有相对较低的幅度和长的持续时间。可以基于存储器单元的擦除深度和诸如编程擦除周期的计数，擦除验证迭代的计数，下部尾部的位置的感测以及交叉点的交叉的因素来调整正的控制栅极电压，存储孔的垂直柱的截面宽度。

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