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1. 发明申请

WO2008083162A1 RETENTION MARGIN PROGRAM VERIFICATION 审中-公开
标题翻译：保留MARGIN程序验证
公开(公告)号：WO2008083162A1
公开(公告)日：2008-07-10
申请号：PCT/US2007/088831
申请日：2007-12-26
申请人： SANDISK CORPORATION , WAN, Jun , LUTZE, Jeffrey, W. , CHEN, Jian , LI, Yan , MAK, Alex
发明人： WAN, Jun , LUTZE, Jeffrey, W. , CHEN, Jian , LI, Yan , MAK, Alex
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3436 , G11C2211/5621
摘要： A memory system, comprising an array of storage elements divided into logical blocks and pages within said logical blocks and a managing circuit is provided. The managing circuit is in communication with said array of storage elements and performs programming and reading operations. The programming operations include programming a plurality of multi-state storage data. The reading operations include defining an retention margin between adjacent data thresholds, determining whether bits are present in a portion of the data retention margin, and if the number of bits in the portion of retention margin exceeds a threshold, generating an error.
摘要翻译：一种存储器系统，包括被划分成逻辑块的存储元件阵列和所述逻辑块内的页面，以及管理电路。管理电路与所述存储元件阵列通信并执行编程和读取操作。编程操作包括编程多个多状态存储数据。读取操作包括定义相邻数据阈值之间的保留余量，确定位是否存在于数据保留余量的一部分中，以及如果保留余量部分中的位数超过阈值，则产生错误。

2. 发明申请

WO2011062917A1 DATA CODING FOR IMPROVED ECC EDDICIENCY IN A NONVOLATILE STORAGE SYSTEM 审中-公开
标题翻译：在非易失存储系统中改进ECC编码的数据编码
公开(公告)号：WO2011062917A1
公开(公告)日：2011-05-26
申请号：PCT/US2010/056900
申请日：2010-11-16
申请人： SANDISK CORPORATION , WAN, Jun , MAK, Alex , KUO, Tien-chien , LI, Yan , CHEN, Jian
发明人： WAN, Jun , MAK, Alex , KUO, Tien-chien , LI, Yan , CHEN, Jian
IPC分类号： G11C11/56
CPC分类号： G11C11/5642 , G11C11/5628 , G11C29/00
摘要： Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing "n" pages of data to be programmed into a group of non-volatile storage elements. The "n" pages are mapped to a data state for each of the non- volatile storage elements based on a coding scheme that evenly distributes read errors across the "n" pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the "n" pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.
摘要翻译：这里描述了用于操作非易失性存储器的非易失性存储设备和技术。一个实施例包括访问要编程到一组非易失性存储元件的“n”页数据。基于在“n”个数据页均匀地分配读取错误的编码方案，将“n”个页面映射到每个非易失性存储元件的数据状态。基于已经映射了多个页面的数据状态，组中的每个非易失性存储元件被编程到阈值电压范围。编程可以包括同时对“n”页进行编程。在一个实施例中，映射多个页面是基于将显着的故障模式（例如，程序干扰错误）分配给第一页面的编码方案以及将重大故障模式（例如，数据保留错误）分配给第二页。

3. 发明申请

WO2013043602A2 HIGH ENDURANCE NON-VOLATILE STORAGE 审中-公开
标题翻译：高耐久性非挥发性储存
公开(公告)号：WO2013043602A2
公开(公告)日：2013-03-28
申请号：PCT/US2012/055919
申请日：2012-09-18
申请人： SANDISK TECHNOLOGIES, INC. , CHEN, Jian , GOROBETS, Sergei , SPROUSE, Steven , KUO, Tien-chien , LI, Yan , LEE, Seungpil , MAK, Alex , DUTTA, Deepanshu , HIGASHITANI, Masaaki
发明人： CHEN, Jian , GOROBETS, Sergei , SPROUSE, Steven , KUO, Tien-chien , LI, Yan , LEE, Seungpil , MAK, Alex , DUTTA, Deepanshu , HIGASHITANI, Masaaki
IPC分类号： G11C16/10 , G11C11/56 , G11C5/06
CPC分类号： G11C16/10 , G11C5/063 , G11C11/5628 , G11C2211/5641
摘要： A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.
摘要翻译：公开了一种非易失性存储系统，其包括设计用于高耐久性和比其他非易失性存储器单元更低保持性的非易失性存储器单元。

4. 发明申请

WO2008157084A1 PROGRAMMABLE CHIP ENABLE AND CHIP ADDRESS IN SEMICONDUCTOR MEMORY 审中-公开
标题翻译：半导体存储器中的可编程芯片使能和芯片地址
公开(公告)号：WO2008157084A1
公开(公告)日：2008-12-24
申请号：PCT/US2008/066111
申请日：2008-06-06
申请人： SANDISK CORPORATION , TU, Loc , CHEN, Jian , MAK, Alex , KUO, Tien-chien , LONG, Pham
发明人： TU, Loc , CHEN, Jian , MAK, Alex , KUO, Tien-chien , LONG, Pham
IPC分类号： G11C16/34 , G11C16/10 , G11C16/08
CPC分类号： G11C29/88 , G11C5/04 , G11C16/04 , G11C29/76 , G11C29/886
摘要： Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.
摘要翻译：存储器管芯具有可编程芯片使能电路，以允许在封装和/或可编程芯片地址电路之后禁止特定存储器管芯，以允许特定存储器管芯在封装之后被读取。在多芯片存储器封装中，可以通过可覆盖从控制器或主机设备接收的主芯片使能信号的可编程电路来禁止与存储器封装隔离的封装级测试失败的存储器管芯。为了提供连续的地址范围，可以使用替代由焊盘键合提供的唯一芯片地址的另一个可编程电路来重新寻址无缺陷存储器管芯中的一个或多个。封装后的存储器芯片也可以被独立于检测出错的存储器芯片而被读取。

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