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1. 发明申请

WO2008089153A2 METHODS OF FORMING SPACER PATTERNS USING ASSIST LAYER FOR HIGH DENSITY SEMICONDUCTOR DEVICES 审中-公开
标题翻译：使用辅助层形成高密度半导体器件的间隔图案的方法
公开(公告)号：WO2008089153A2
公开(公告)日：2008-07-24
申请号：PCT/US2008/051017
申请日：2008-01-14
申请人： SANDISK CORPORATION , KAI, James , METAMIS, George , PHAM, Tuan, Duc , HIGASHITANI, Masaaki , ORIMOTO, Takashi
发明人： KAI, James , METAMIS, George , PHAM, Tuan, Duc , HIGASHITANI, Masaaki , ORIMOTO, Takashi
IPC分类号： H01L21/033 , H01L21/28 , H01L21/308 , H01L21/8247 , H01L27/115
CPC分类号： H01L21/28273 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/32139 , H01L27/115 , H01L27/11521
摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.
摘要翻译：提供了高密度半导体器件及其制造方法。利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻可分辨的元件尺寸。形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

2. 发明申请

WO2011011525A1 METHOD OF FORMING NANOSTRUCTURE-BASED NAND FLASH CELLS AND THE PERIPHERY CIRCUITS THEREOF 审中-公开
标题翻译：形成基于纳米结构的NAND闪存细胞及其周围电路的方法
公开(公告)号：WO2011011525A1
公开(公告)日：2011-01-27
申请号：PCT/US2010/042766
申请日：2010-07-21
申请人： SANDISK CORPORATION , PURAYATH, Vinod, Robert , KAI, James, K. , HIGASHITANI, Masaaki , ORIMOTO, Takashi , MATAMIS, George , CHIEN, Henry
发明人： PURAYATH, Vinod, Robert , KAI, James, K. , HIGASHITANI, Masaaki , ORIMOTO, Takashi , MATAMIS, George , CHIEN, Henry
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115
CPC分类号： H01L21/76224 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/11526 , H01L27/11529 , H01L27/11536 , H01L27/11546 , H01L27/11573 , H01L29/788 , Y10S438/962 , Y10S977/774 , Y10S977/936
摘要： Nanostructure-based charge storage regions (CSR1-CSR5) are included in non-volatile memory devices and integrated with the fabrication of select gates (SGl) and peripheral circuitry (PGl, PG2) One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.
摘要翻译：基于纳米结构的电荷存储区域（CSR1-CSR5）被包括在非易失性存储器件中，并与选择栅极（SG1）和外围电路（PG1，PG2）的制造集成在一个衬底上施加一个或多个纳米结构涂层存储器阵列区域和外围电路区域。提供了用于从衬底的不需要的区域（例如选择栅极和外围晶体管的目标区域）去除纳米结构涂层的各种工艺。在一个实例中，使用基于自组装的工艺来形成一个或多个纳米结构涂层以在衬底的有源区上选择性地形成纳米结构。自组装允许形成彼此电隔离的纳米结构的离散线，而不需要对纳米结构涂层进行图案化或蚀刻。

3. 发明申请

WO2008122012A2 INTEGRATED NON-VOLATILE MEMORY AND PERIPHERAL CIRCUITRY FABRICATION 审中-公开
标题翻译：集成的非易失性存储器和外围电路制造
公开(公告)号：WO2008122012A2
公开(公告)日：2008-10-09
申请号：PCT/US2008/059035
申请日：2008-04-01
申请人： SANDISK CORPORATION , KAI, James , PHAM, Tuan , HIGASHITANI, Masaaki , MATAMIS, George , ORIMOTO, Takashi
发明人： KAI, James , PHAM, Tuan , HIGASHITANI, Masaaki , MATAMIS, George , ORIMOTO, Takashi
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115
CPC分类号： H01L27/11529 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11536 , H01L27/11539
摘要： Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.
摘要翻译：提供非易失性存储器和集成存储器和外围电路制造工艺。使用诸如第一多晶硅层的电荷存储材料层在半导体衬底上形成诸如包括多个非易失性存储元件的NAND串的电荷存储区的集合。中间电介质层设置在电荷存储区域的上方。将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于存储元件组的选择晶体管的电荷存储区域和栅极区域的控制栅极。从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。这些器件的栅极区域可以由形成存储器阵列的控制栅极的层形成。

4. 发明申请

WO2009129053A1 NON-VOLATILE MEMORY WITH SIDEWALL CHANNELS AND RAISED SOURCE/DRAIN REGIONS 审中-公开
标题翻译：非易失性存储器，带有通道和扩展源/漏区
公开(公告)号：WO2009129053A1
公开(公告)日：2009-10-22
申请号：PCT/US2009/039202
申请日：2009-04-01
申请人： SANDISK CORPORATION , CHIEN, Henry , PURAYATH, Vinod, R. , KAI, James , MATAMIS, George , ORIMOTO, Takashi
发明人： CHIEN, Henry , PURAYATH, Vinod, R. , KAI, James , MATAMIS, George , ORIMOTO, Takashi
IPC分类号： G11C11/56 , G11C11/16
CPC分类号： G11C8/10 , G11C8/04 , G11C11/5621 , G11C16/0483 , G11C19/00 , H01L21/28273 , H01L27/11521
摘要： A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.
摘要翻译：一种非易失性存储系统，其中浮动栅极的侧壁绝缘层比底部绝缘层的厚度明显薄，并且其中设置有凸起的源极/漏极区域。在编程或擦除期间，隧道主要通过侧壁绝缘层和凸起的源极/漏极区域而不是通过底部绝缘层发生。浮动门可以具有均匀的宽度或倒T形。凸起的源极/漏极区域可以从衬底外延生长，并且可以包括在未掺杂区域上方的掺杂区域，使得沟道长度从浮置栅极下方有效地延伸并且向上延伸到未掺杂区域，使得短沟道效应为降低。侧壁绝缘层与底部绝缘层的厚度的比可以为约0.3〜0.67。

5. 发明申请

WO2008088654A1 NAND MEMORY WITH DUAL CONTROL GATES HAVING FIXED CHARGE LAYER BELOW CONTROL GATES 审中-公开
标题翻译：具有双控制门的NAND存储器具有下面的固定充电层下面的控制门
公开(公告)号：WO2008088654A1
公开(公告)日：2008-07-24
申请号：PCT/US2007/088145
申请日：2007-12-19
申请人： SANDISK CORPORATION , CHIEN, Henry , MATAMIS, George , ORIMOTO, Takashi , KAI, James
发明人： CHIEN, Henry , MATAMIS, George , ORIMOTO, Takashi , KAI, James
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/51
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/66825
摘要： A string (200) of nonvolatile memory cells are connected together by source/drain regions (202-205)- that include an inversion layer created by fixed charge in an overlying layer (210-213). Control gates (220-223) extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation. Fixed charges may also be located between floating gates and the underlying substrate surface. Fixed charge over source/drain regions and under floating gates are formed together in a common deposition.
摘要翻译：非易失性存储单元的串（200）由源/漏区（202-205）连接在一起，包括在上层（210-213）中由固定电荷产生的反型层。控制栅极（220-223）在浮动栅极之间延伸，使得两个控制栅极耦合到浮动栅极。可以通过等离子体氮化形成固定电荷层。固定电荷也可以位于浮动栅极和下面的衬底表面之间。源极/漏极区域和浮置栅极之间的固定电荷一起形成在共同的沉积中。

6. 发明申请

WO2011091416A1 DAMASCENE METHOD OF MAKING A NONVOLATILE MEMORY DEVICE 审中-公开
标题翻译：制造非易失性存储器件的DAMASCENE方法
公开(公告)号：WO2011091416A1
公开(公告)日：2011-07-28
申请号：PCT/US2011/022400
申请日：2011-01-25
申请人： SANDISK 3D LLC , PURAYATH, Vinod Robert , MATAMIS, George , KAI, James , ORIMOTO, Takashi
发明人： PURAYATH, Vinod Robert , MATAMIS, George , KAI, James , ORIMOTO, Takashi
IPC分类号： H01L27/10 , H01L27/102
CPC分类号： H01L27/101 , H01L27/1021
摘要： A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.
摘要翻译：一种制造器件的方法包括提供包含由第一绝缘特征分开的第一半导体轨道的第一器件电平，在第一器件电平上形成牺牲层，在第一器件电平图形化牺牲层和第一半导体轨道以形成多个的第二轨道沿着第二方向延伸，其中所述多个第二轨道至少部分地延伸到所述第一装置水平面并且通过至少部分地延伸到所述第一装置水平的轨道形开口彼此分开，所述多个第二轨道，去除所述牺牲层，以及在所述第二设备水平上的第二设备水平的所述第二绝缘特征之间形成第二半导体轨道。第一半导体轨道沿第一方向延伸。第二半导体轨道沿与第一方向不同的第二方向延伸。

7. 发明申请

WO2010059296A1 SELF-ALIGNED THREE-DIMENSIONAL NON-VOLATILE MEMORY FABRICATION 审中-公开
标题翻译：自对准的三维非易失性存储器制造
公开(公告)号：WO2010059296A1
公开(公告)日：2010-05-27
申请号：PCT/US2009/059052
申请日：2009-09-30
申请人： SANDISK 3D LLC , MATAMIS, George , CHIEN, Henry , KAI, James, K. , ORIMOTO, Takashi , PURAYATH, Vinod, R. , PING, Er-Xuan , SCHEUERLEIN, Roy, E.
发明人： MATAMIS, George , CHIEN, Henry , KAI, James, K. , ORIMOTO, Takashi , PURAYATH, Vinod, R. , PING, Er-Xuan , SCHEUERLEIN, Roy, E.
IPC分类号： G11C16/02 , H01L21/822 , H01L27/06 , H01L27/24
CPC分类号： H01L21/20 , G11C13/0004 , G11C17/16 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.
摘要翻译：公开了一种用于三维非易失性存储器的自对准制造工艺。双重蚀刻工艺在与导体下面和上面的记忆柱自对准的给定水平处形成导体。以这种方式形成导体可以包括使用沿给定方向的第一重复图案蚀刻第一导体层以形成导体的第一部分。具有第一图案的蚀刻还限定了下面的柱结构的两个相对的侧壁，从而使导体与支柱自对准。蚀刻后，沉积第二导体层，随后沉积半导体层堆叠。执行以与第一图案相同的方向重复的第二图案的蚀刻，从而形成与上层叠层线自对准的导体的第二部分。然后将这些层堆叠线正交蚀刻以限定覆盖导体的第二组支柱。

8. 发明申请

WO2008011053A1 MEMORY CELL SYSTEM WITH CHARGE TRAP 审中-公开
标题翻译：带有电荷捕获的存储单元系统
公开(公告)号：WO2008011053A1
公开(公告)日：2008-01-24
申请号：PCT/US2007/016250
申请日：2007-07-17
申请人： SPANSION LLC , ADVANCED MICRO DEVICES, INC. , DING, Meng , JOSHI, Amol, Ramesh , XUE, Lei , ORIMOTO, Takashi , CHANG, Kuo-Tung
发明人： DING, Meng , JOSHI, Amol, Ramesh , XUE, Lei , ORIMOTO, Takashi , CHANG, Kuo-Tung
IPC分类号： H01L21/28 , H01L29/51 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11563 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/513 , H01L29/792
摘要： A memory cell system (1000) is provided including forming a first insulator layer (212) over a semiconductor substrate (204), forming a charge trap layer (216) over the first insulator layer (212), forming an intermediate layer (218) over the charge trap layer (216), and forming a second insulator layer (220) with the intermediate layer (218).
摘要翻译：提供一种存储单元系统（1000），包括在半导体衬底（204）上形成第一绝缘体层（212），在第一绝缘体层（212）上形成电荷陷阱层（216），形成中间层（218）在所述电荷陷阱层（216）之上，以及与所述中间层（218）形成第二绝缘体层（220）。

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