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1. 发明申请

WO2006105133A1 SOFT PROGRAMMING NON-VOLATILE MEMORY UTILIZING INDIVIDUAL VERIFICATION AND ADDITIONAL SOFT PROGRAMMING OF SUBSETS OF MEMORY CELLS 审中-公开
标题翻译：使用个人验证的软件编程非易失性存储器和存储器存储器的附加软件编程
公开(公告)号：WO2006105133A1
公开(公告)日：2006-10-05
申请号：PCT/US2006/011354
申请日：2006-03-29
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , KAMEI, Teruhiko
发明人： HEMINK, Gerrit, Jan , KAMEI, Teruhiko
IPC分类号： G11C16/34
CPC分类号： G11C16/3409 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/345 , G11C16/3454 , G11C16/3468 , G11C16/3472 , G11C16/3477 , G11C2211/5621 , G11C2216/18
摘要： A set of non-volatile storage elements is divided into subsets for soft programming in order to more fully soft-program slower soft programming elements. The entire set of elements is soft-programmed until verified as soft programmed (or until a first subset of elements is verified as soft programmed while excluding a second subset from verification). After the set is verified as soft programmed, a first subset of elements is inhibited from further soft programming while additional soft programming is carried out on a second subset of elements. The second subset can include slower soft programming elements. The second subset can then undergo soft programming verification while excluding the first subset from verification. Soft programming and verifying for the second subset can continue until it is verified as soft programmed. Different step sizes can be used for increasing the size of the soft programming signal, depending on which subset is being soft programmed and verified.
摘要翻译：一组非易失性存储元件被划分为用于软编程的子集，以便更软地编程较慢的软编程元件。整个元素组被软编程，直到被验证为软编程（或直到第一个元素子集被验证为软编程，而不是第二个子集来验证）。在集合被验证为软编程之后，元素的第一子集被禁止进一步的软编程，而在第二子元素上执行附加的软编程。第二子集可以包括较慢的软编程元素。然后可以将第二个子集进行软编程验证，同时将第一个子集排除在验证之外。软编程和验证第二个子集可以继续，直到它被验证为软编程。可以使用不同的步长来增加软编程信号的大小，具体取决于软编程和验证哪个子集。

2. 发明申请

WO2009006485A1 ERASE VOLTAGE MANIPULATION IN NON-VOLATILE MEMORY FOR CONTROLLED SHIFTS IN THRESHOLD VOLTAGE 审中-公开
标题翻译：用于控制电压的非易失性存储器中的电压调节在阈值电压
公开(公告)号：WO2009006485A1
公开(公告)日：2009-01-08
申请号：PCT/US2008/068939
申请日：2008-07-01
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , KAMEI, Teruhiko
发明人： HEMINK, Gerrit, Jan , KAMEI, Teruhiko
IPC分类号： G11C11/56 , G11C16/14 , G11C16/34
CPC分类号： G11C11/5635 , G11C16/0483 , G11C16/16 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C2211/5621
摘要： The erase voltage applied to a set of non-volatile storage elements being erased is structured to provide controlled shifts in the threshold voltage of the storage elements. The erase voltage is applied as a series of voltage pulses, when necessary, to shift the threshold voltage of to-be-erased memory cells below a verify level indicative of an erased condition. To avoid over-erasing the memory cells, the second erase voltage pulse is decreased, or not increased, in magnitude when compared to the previously applied voltage pulse. By decreasing or not increasing the size of the erase voltage, the amount of charge transferred from the cells by the second pulse is controlled to more accurately position an erased threshold voltage distribution for the cells near the verify level. Subsequent erase voltage pulses are increased in magnitude to provide further erasing when needed.
摘要翻译：施加到被擦除的一组非易失性存储元件的擦除电压被构造成提供存储元件的阈值电压的受控偏移。当需要时，将擦除电压作为一系列电压脉冲施加以将被擦除的存储器单元的阈值电压移动到指示擦除状态的验证电平以下。为了避免过度擦除存储单元，与先前施加的电压脉冲相比，第二擦除电压脉冲的幅度减小或不增加。通过减小或不增加擦除电压的大小，控制从单元传输的第二脉冲的电荷量，以更准确地定位靠近验证电平的单元的擦除的阈值电压分布。随后的擦除电压脉冲的幅度增大，以便在需要时进一步擦除。

3. 发明申请

WO2006105120A1 ERASING NON-VOLATILE MEMORY USING INDIVIDUAL VERIFICATION AND ADDITIONAL ERASING OF SUBSETS OF MEMORY CELLS 审中-公开
标题翻译：使用个人验证和附加擦除存储器细胞的次序擦除非易失性记忆
公开(公告)号：WO2006105120A1
公开(公告)日：2006-10-05
申请号：PCT/US2006/011340
申请日：2006-03-29
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , KAMEI, Teruhiko
发明人： HEMINK, Gerrit, Jan , KAMEI, Teruhiko
IPC分类号： G11C16/34
CPC分类号： G11C16/344 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3468 , G11C16/3472 , G11C16/3477 , G11C2211/5621 , G11C2216/18
摘要： A set of non-volatile storage elements is divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements. The entire set of elements is erased until a first subset of the set of elements is verified as erased. The first subset can include the faster erasing cells. Verifying the first subset includes excluding a second subset from verification. After the first subset is verified as erased, they are inhibited from erasing while the second subset is further erased. The set of elements is verified as erased when the second subset is verified as erased. Verifying that the set of elements is erased can include excluding the first subset from verification or verifying both the first and second subsets together. Different step sizes are used, depending on which subset is being erased and verified in order to more efficiently and accurately erase the set of elements.
摘要翻译：一组非易失性存储元件被划分成用于擦除的子集，以避免擦除存储元件的擦除更快。整个元素组被擦除，直到该组元素的第一个子集被验证为被擦除为止。第一个子集可以包括更快的擦除单元。验证第一个子集包括从验证中排除第二个子集。在第一子集被验证为擦除之后，它们被禁止擦除，而第二子集被进一步擦除。当第二个子集被验证为擦除时，该组元素被验证为被擦除。验证该组元素被擦除可以包括排除第一子集验证或验证第一和第二子集在一起。使用不同的步长，这取决于要擦除和验证哪个子集，以便更有效和准确地擦除该组元素。

4. 发明申请

WO2011066234A1 PROGRAMMING NON-VOLATILE MEMORY WITH REDUCED NUMBER OF VERIFY OPERATIONS 审中-公开
标题翻译：编程非易失性存储器，具有减少的验证数量
公开(公告)号：WO2011066234A1
公开(公告)日：2011-06-03
申请号：PCT/US2010/057666
申请日：2010-11-22
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , HEMINK, Gerrit, Jan
发明人： DUTTA, Deepanshu , HEMINK, Gerrit, Jan
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C16/3454 , G11C11/5628 , G11C16/3459 , G11C2211/5621
摘要： A method and non-volatile storage system are provided in which programming speed is increased by reducing the number of verify operations, while maintaining a narrow threshold voltage distribution. A programming scheme performs a verify operation at an offset level, before a verify level of a target data state is reached, such as to slow down programming. However, it is not necessary to perform verify operations at both the offset and target levels at all times. In a first programming phase, verify operations are performed for a given data state only at the target verify level. In a second programming phase, verify operations are performed for offset and target verify levels. In a third programming phase, verify operations are again performed only at the target verify level. Transitions between phases can be predetermined, based on programming pulse number, or adaptive.
摘要翻译：提供了一种方法和非易失性存储系统，其中通过减少验证操作的数量来增加编程速度，同时保持窄的阈值电压分布。在达到目标数据状态的验证级别之前，编程方案在偏移级别执行验证操作，例如减慢编程。但是，始终不必在偏移量和目标电平两者上执行验证操作。在第一个编程阶段，仅在目标验证级别对给定数据状态执行验证操作。在第二个编程阶段，对偏移和目标验证电平执行验证操作。在第三个编程阶段，仅在目标验证级别再次执行验证操作。相位之间的转换可以根据编程脉冲数或自适应来预先确定。

5. 发明申请

WO2008137687A1 BOOSTING FOR NON-VOLATILE STORAGE USING CHANNEL ISOLATION SWITCHING 审中-公开
标题翻译：使用通道隔离开关来促进非易失性存储
公开(公告)号：WO2008137687A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/062432
申请日：2008-05-02
申请人： SANDISK CORPORATION , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Shih-Chung , HEMINK, Gerrit, Jan , OOWADA, Ken
发明人： DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Shih-Chung , HEMINK, Gerrit, Jan , OOWADA, Ken
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.
摘要翻译：在非易失性存储器中通过防止所选择的NAND串中的源极升压来减少编程干扰。使用包括隔离字线的自增强模式。禁止的NAND串的通道区域在隔离字线的漏极侧的通道升压之前在隔离字线的源极侧被升压。此外，在源侧升压期间，隔离字线附近的存储元件保持导通状态，使得源极侧沟道连接到漏极侧沟道。以这种方式，在选择的NAND串中，不能发生源侧升压，因此可以防止由于源极侧升压而导致的编程干扰。在源侧升压之后，源侧沟道与漏极侧沟道隔离，并且进行漏极侧升压。

6. 发明申请

WO2006107730A1 COMPENSATING FOR COUPLING IN NON-VOLATILE STRORAGE 审中-公开
标题翻译：非易失性连接中的耦合补偿
公开(公告)号：WO2006107730A1
公开(公告)日：2006-10-12
申请号：PCT/US2006/011811
申请日：2006-03-31
申请人： SANDISK CORPORATION , CHEN, Jian , CERNEA, Raul-Adrian , HEMINK, Gerrit, Jan
发明人： CHEN, Jian , CERNEA, Raul-Adrian , HEMINK, Gerrit, Jan
IPC分类号： G11C11/56 , G11C16/26 , G11C16/34
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/26 , G11C16/3418 , G11C16/3422 , G11C16/3431
摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.
摘要翻译：存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合）。在不同时间编程的相邻存储器单元组之间最明显地出现该问题。为了补偿该耦合，给定存储单元的读取过程将考虑相邻存储器单元的编程状态。

7. 发明申请

WO2010047925A1 PROGRAMMING NON-VOLATILE MEMORY WITH VARIABLE INITIAL PROGRAMMING PULSE 审中-公开
标题翻译：编程具有可变初始编程脉冲的非易失性存储器
公开(公告)号：WO2010047925A1
公开(公告)日：2010-04-29
申请号：PCT/US2009/058874
申请日：2009-09-29
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan
发明人： HEMINK, Gerrit, Jan
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3468 , G11C16/3486 , G11C2211/5621 , G11C2211/5648
摘要： Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of the non-volatile storage elements to a set of target conditions using programming pulses. For at least a subset of the programming processes, a programming pulse associated with achieving an intermediate result for a respective programming process is identified, a pulse increment between programming pulses is decreased for the respective programming process while continuing the respective programming process to program non-volatile storage elements to the respective one or more targets and the identified programming pulse is used to adjust a starting programming voltage for a subsequent programming process.
摘要翻译：对多个非易失性存储元件执行多个编程处理。编程过程中的每一个操作以使用编程脉冲将至少一个非易失性存储元件的子集编程到一组目标条件。对于编程过程的至少一个子集，识别与实现相应编程处理的中间结果相关联的编程脉冲，针对相应的编程过程减少编程脉冲之间的脉冲增量，同时继续相应的编程处理，易失性存储元件到相应的一个或多个目标，并且所识别的编程脉冲用于调整用于后续编程处理的起始编程电压。

8. 发明申请

WO2009148906A1 ERASE-VERIFICATION PROCESS FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：非易失性存储的擦除验证过程
公开(公告)号：WO2009148906A1
公开(公告)日：2009-12-10
申请号：PCT/US2009/045358
申请日：2009-05-28
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , LEE, Shih-Chung , MIWA, Toru , FONG, Yupin , WAN, Jun , OOWADA, Ken
发明人： HEMINK, Gerrit, Jan , LEE, Shih-Chung , MIWA, Toru , FONG, Yupin , WAN, Jun , OOWADA, Ken
IPC分类号： G11C16/34
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non- volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non- volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功地擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

9. 发明申请

WO2009143435A1 ENHANCED BIT-LINE PRE-CHARGE SCHEME FOR INCREASING CHANNEL BOOSTING IN NON-VOLATILE STORAGE 审中-公开
标题翻译：增强非易失性存储器中的通道增强的双线预先计费方案
公开(公告)号：WO2009143435A1
公开(公告)日：2009-11-26
申请号：PCT/US2009/044999
申请日：2009-05-22
申请人： SANDISK CORPORATION , DONG, Yingda , MUI, Man, L. , LUTZE, Jeffrey, W. , SATO, Shinji , HEMINK, Gerrit, Jan
发明人： DONG, Yingda , MUI, Man, L. , LUTZE, Jeffrey, W. , SATO, Shinji , HEMINK, Gerrit, Jan
IPC分类号： G11C11/56 , G11C16/10 , G11C16/12
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/32 , G11C16/3418 , G11C16/3427
摘要： Channel boosting is improved in non-volatile storage to reduce program disturb. A pre-charge module voltage source is used to pre-charge bit lines during a programming operation. The pre-charge module voltage source is coupled to a substrate channel via the bit lines to boost the channel. An additional source of boosting is provided by electromagnetically coupling a voltage from a conductive element to the bit lines and the channel. To achieve this, the bit lines and the channel are allowed to float together by disconnecting the bit lines from the voltage sources. The conductive element can be a source line, power supply line or substrate body, for instance, which receives an increasing voltage during the pre-charging and is proximate to the bit lines.
摘要翻译：在非易失性存储器中改善通道增强以减少程序干扰。预充电模块电压源用于在编程操作期间预充电位线。预充电模块电压源通过位线耦合到衬底通道以升高通道。通过将来自导电元件的电压电磁耦合到位线和通道来提供额外的升压源。为了实现这一点，通过将位线与电压源断开来允许位线和通道浮动在一起。导电元件可以是例如在预充电期间接收增加的电压并且靠近位线的源极线，电源线或衬底主体。

10. 发明申请

WO2008039667A2 REDUCING PROGRAM DISTURB IN NON-VOLATILE STORAGE 审中-公开
标题翻译：减少非易失性存储中的程序干扰
公开(公告)号：WO2008039667A2
公开(公告)日：2008-04-03
申请号：PCT/US2007/078842
申请日：2007-09-19
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , LEE, Shih-chung
发明人： HEMINK, Gerrit, Jan , LEE, Shih-chung
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C2211/5621
摘要： A non-volatile semiconductor storage system is programmed in a manner that reduces program disturb by applying a higher boosting voltage on one or more word lines that are connected non-volatile storage elements that may be partially programmed.
摘要翻译：非易失性半导体存储系统以这样的方式编程：通过在连接到可被部分编程的非易失性存储元件的一条或多条字线上施加较高升压电压来减少编程干扰。

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