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1. 发明申请

WO2009148906A1 ERASE-VERIFICATION PROCESS FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：非易失性存储的擦除验证过程
公开(公告)号：WO2009148906A1
公开(公告)日：2009-12-10
申请号：PCT/US2009/045358
申请日：2009-05-28
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , LEE, Shih-Chung , MIWA, Toru , FONG, Yupin , WAN, Jun , OOWADA, Ken
发明人： HEMINK, Gerrit, Jan , LEE, Shih-Chung , MIWA, Toru , FONG, Yupin , WAN, Jun , OOWADA, Ken
IPC分类号： G11C16/34
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non- volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non- volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功地擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

2. 发明申请

WO2008157606A1 INTELLIGENT CONTROL OF PROGRAM PULSE DURATION 审中-公开
标题翻译：智能控制程序脉冲持续时间
公开(公告)号：WO2008157606A1
公开(公告)日：2008-12-24
申请号：PCT/US2008/067347
申请日：2008-06-18
申请人： SANDISK CORPORATION , FONG, Yupin , WAN, Jun
发明人： FONG, Yupin , WAN, Jun
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached. At that point, the magnitude of the programming pulses stops increasing and the programming pulses are applied in a manner to provide varying time duration of the programming signal between verification operations. In one embodiment, for example, after the pulses reach the maximum magnitude the pulse widths are increased. In another embodiment, after the pulses reach the maximum magnitude multiple program pulses are applied between verification operations.
摘要翻译：为了对一组非易失性存储元件进行编程，将一组编程脉冲施加到非易失性存储元件的控制门（或其它终端）。编程脉冲具有恒定的脉冲宽度和增加的幅度，直到达到最大电压。在这一点上，编程脉冲的幅度停止增加，编程脉冲以一种方式施加，以便在验证操作之间提供编程信号的变化的持续时间。在一个实施例中，例如，在脉冲达到最大幅度之后，脉冲宽度增加。在另一个实施例中，在脉冲达到最大幅度之后，在验证操作之间施加多个编程脉冲。

3. 发明申请

WO2007067447A1 REDUCING READ DISTURB FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：减少读取干扰非易失性存储
公开(公告)号：WO2007067447A1
公开(公告)日：2007-06-14
申请号：PCT/US2006/046126
申请日：2006-11-30
申请人： SANDISK CORPORATION , FONG, Yupin , WAN, Jun , LUTZE, Jeffrey
发明人： FONG, Yupin , WAN, Jun , LUTZE, Jeffrey
IPC分类号： G11C16/04 , G11C16/34
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C16/3459 , G11C2211/5642
摘要： A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.
摘要翻译：公开了一种用于减少或去除非易失性存储装置中的读取干扰形式的系统。一个实施例旨在通过消除或最小化存储器元件的通道的升高来防止读取干扰。例如，一个实施方式在读取过程期间防止或减少NAND串通道的源极侧的升压。因为NAND串通道的源极侧不被提升，所以读取干扰的至少一种形式被最小化或不发生。

4. 发明申请

WO2007016167A1 PROGRAMMING NON-VOLATILE MEMORY WITH SELF-ADJUSTING MAXIMUM PROGRAM LOOP 审中-公开
标题翻译：使用自调整最大程序循环编程非易失性存储器
公开(公告)号：WO2007016167A1
公开(公告)日：2007-02-08
申请号：PCT/US2006/029047
申请日：2006-07-26
申请人： SANDISK CORPORATION , WAN, Jun , LUTZE, Jeffrey, W.
发明人： WAN, Jun , LUTZE, Jeffrey, W.
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/12 , G11C16/3454 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50004 , G11C2029/0409
摘要： The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elements reaches a certain verify level, after which a defined maximum number of additional pulses may be applied to other memory elements to allow them to also reach associated target threshold voltage levels. The technique enforces a maximum allowable number of programming pulses that can change over time as the memory is cycled.
摘要翻译：调整非易失性存储器件对程序存储器元件的电压编程脉冲的最大允许数量，以便考虑随时间发生的存储元件的变化。施加编程脉冲，直到一个或多个存储器元件的阈值电压达到某个验证电平，之后可以将限定的最大数量的附加脉冲施加到其它存储器元件以允许它们也达到相关联的目标阈值电压电平。该技术实现了随着存储器循环而随时间变化的最大允许编程脉冲数。

5. 发明申请

WO2011062917A1 DATA CODING FOR IMPROVED ECC EDDICIENCY IN A NONVOLATILE STORAGE SYSTEM 审中-公开
标题翻译：在非易失存储系统中改进ECC编码的数据编码
公开(公告)号：WO2011062917A1
公开(公告)日：2011-05-26
申请号：PCT/US2010/056900
申请日：2010-11-16
申请人： SANDISK CORPORATION , WAN, Jun , MAK, Alex , KUO, Tien-chien , LI, Yan , CHEN, Jian
发明人： WAN, Jun , MAK, Alex , KUO, Tien-chien , LI, Yan , CHEN, Jian
IPC分类号： G11C11/56
CPC分类号： G11C11/5642 , G11C11/5628 , G11C29/00
摘要： Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing "n" pages of data to be programmed into a group of non-volatile storage elements. The "n" pages are mapped to a data state for each of the non- volatile storage elements based on a coding scheme that evenly distributes read errors across the "n" pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the "n" pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.
摘要翻译：这里描述了用于操作非易失性存储器的非易失性存储设备和技术。一个实施例包括访问要编程到一组非易失性存储元件的“n”页数据。基于在“n”个数据页均匀地分配读取错误的编码方案，将“n”个页面映射到每个非易失性存储元件的数据状态。基于已经映射了多个页面的数据状态，组中的每个非易失性存储元件被编程到阈值电压范围。编程可以包括同时对“n”页进行编程。在一个实施例中，映射多个页面是基于将显着的故障模式（例如，程序干扰错误）分配给第一页面的编码方案以及将重大故障模式（例如，数据保留错误）分配给第二页。

6. 发明申请

WO2007030536A1 LAST-FIRST MODE AND METHOD FOR PROGRAMMING OF NON-VOLATILE MEMORY OF NAND TYPE WITH REDUCED PROGRAM DISTURB 审中-公开
标题翻译：用于编程具有减少的程序间隔的NAND类型的非易失性存储器的最初的模式和方法
公开(公告)号：WO2007030536A1
公开(公告)日：2007-03-15
申请号：PCT/US2006/034711
申请日：2006-09-06
申请人： SANDISK CORPORATION , WAN, Jun , LUTZE, Jeffrey, W.
发明人： WAN, Jun , LUTZE, Jeffrey, W.
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C2211/5648
摘要： A non-volatile memory of NAND type is programmed in a manner which reduces the incidence of program disturb for inhibited memory elements which undergo boosting to reduce program disturb, but which experience reduced boosting benefits due to their word line location. To achieve this result, a word line sequence in which the memory elements are programmed is adjusted so that higher word lines are programmed first, out of sequence relative to the remaining word lines. Additionally, self-boosting can be used for the higher word lines, while erased area self-boosting or a variant can be used for the remaining word lines. Furthermore, pre-charging of the channel of the inhibited memory elements may be employed prior to the self boosting, for the non volatile storage elements which are programmed after those associated with the first word line.
摘要翻译： NAND类型的非易失性存储器以减少对被抑制的存储器元件的发生率的方式进行编程，所述禁止存储器元件经历升压以减少编程干扰，但是哪些经历减少了由于其字线位置引起的益处。为了实现该结果，调整存储器元件被编程的字线序列，使得较高的字线首先被编程，而不是相对于剩余字线的顺序。此外，自增强可以用于较高字线，而擦除区域自增强或变体可用于剩余的字线。此外，对于在与第一字线相关联的那些之后编程的非易失性存储元件，可以在自增强之前采用禁止的存储器元件的通道的预充电。

7. 发明申请

WO2011146241A1 ERASE AND PROGRAMMING TECHNIQUES TO REDUCE THE WIDENING OF STATE DISTRIBUTIONS IN NON-VOLATILE MEMORIES 审中-公开
标题翻译：删除和编程技术减少非易失性存储器中状态分布的增加
公开(公告)号：WO2011146241A1
公开(公告)日：2011-11-24
申请号：PCT/US2011/035190
申请日：2011-05-04
申请人： SANDISK CORPORATION , LEI, Bo , LIANG, Guirong , KHANDELWAL, Anubhav , WAN, Jun
发明人： LEI, Bo , LIANG, Guirong , KHANDELWAL, Anubhav , WAN, Jun
IPC分类号： G11C16/16 , G11C16/34
CPC分类号： G11C16/16 , G11C16/3404
摘要： Techniques are presented for use in memory devices to improve reliability and endurance by reducing the widening in state distributions, that occurs after multiple write/erase cycles. One set of techniques uses a pre-conditioning operation where a pulse series, which may include program and gentle erase, are applied to one or more wordlines while a voltage differential is applied in the wordline direction, bitline direction, or both. Another set of techniques uses a dual or multi-pulse program process, where an increased wordline-to-wordline differential used in the first pulse of a pair.
摘要翻译：提供了用于存储器件的技术，以通过减少在多个写入/擦除周期之后发生的状态分布的扩大来提高可靠性和耐久性。一组技术使用预处理操作，其中可以包括程序和温和擦除的脉冲序列被施加到一个或多个字线，同时在字线方向，位线方向或两者上施加电压差。另一组技术使用双脉冲或多脉冲程序过程，其中在一对的第一脉冲中使用增加的字线对字线差分。

8. 发明申请

WO2008083162A1 RETENTION MARGIN PROGRAM VERIFICATION 审中-公开
标题翻译：保留MARGIN程序验证
公开(公告)号：WO2008083162A1
公开(公告)日：2008-07-10
申请号：PCT/US2007/088831
申请日：2007-12-26
申请人： SANDISK CORPORATION , WAN, Jun , LUTZE, Jeffrey, W. , CHEN, Jian , LI, Yan , MAK, Alex
发明人： WAN, Jun , LUTZE, Jeffrey, W. , CHEN, Jian , LI, Yan , MAK, Alex
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3436 , G11C2211/5621
摘要： A memory system, comprising an array of storage elements divided into logical blocks and pages within said logical blocks and a managing circuit is provided. The managing circuit is in communication with said array of storage elements and performs programming and reading operations. The programming operations include programming a plurality of multi-state storage data. The reading operations include defining an retention margin between adjacent data thresholds, determining whether bits are present in a portion of the data retention margin, and if the number of bits in the portion of retention margin exceeds a threshold, generating an error.
摘要翻译：一种存储器系统，包括被划分成逻辑块的存储元件阵列和所述逻辑块内的页面，以及管理电路。管理电路与所述存储元件阵列通信并执行编程和读取操作。编程操作包括编程多个多状态存储数据。读取操作包括定义相邻数据阈值之间的保留余量，确定位是否存在于数据保留余量的一部分中，以及如果保留余量部分中的位数超过阈值，则产生错误。

9. 发明申请

WO2006071559A1 WORD LINE COMPENSATION IN NON-VOLATILE MEMORY ERASE OPERATIONS 审中-公开
标题翻译：非易失性存储器擦除操作中的字线补偿
公开(公告)号：WO2006071559A1
公开(公告)日：2006-07-06
申请号：PCT/US2005/045557
申请日：2005-12-15
申请人： SANDISK CORPORATION , WAN, Jun , LUTZE, Jeffrey, W. , PANG, Chan-sui
发明人： WAN, Jun , LUTZE, Jeffrey, W. , PANG, Chan-sui
IPC分类号： G11C16/16 , G11C16/04 , G11C16/34
CPC分类号： G11C8/08 , G11C16/0483 , G11C16/16 , G11C16/3468
摘要： Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages capacitively coupled to memory cells of a NAND string from other memory cells and/or select gates. A compensation voltage can be applied to one or more memory cells to substantially normalize the erase behavior of the memory cells. A compensation voltage can be applied to end memory cells of a NAND string to equalize their erase behavior with interior memory cells of the NAND string. A compensation voltage can also be applied to interior memory cells to equalize their erase behavior with end memory cells. Additionally, a compensation voltage can be applied to one or more select gates of a NAND string to compensate for voltages coupled to one or more memory cells from the select gate(s). Various compensation voltages can be used.
摘要翻译：在擦除操作期间，补偿电压施加到非易失性存储器系统以均衡存储器单元的擦除行为。补偿电压可以补偿与其他存储器单元和/或选择栅极的NAND串的存储器单元电容耦合的电压。补偿电压可以施加到一个或多个存储器单元，以基本上规范化存储器单元的擦除行为。可以将补偿电压施加到NAND串的末端存储单元，以使其与NAND串的内部存储单元的擦除行为相等。还可以将补偿电压施加到内部存储器单元，以使其与端部存储器单元的擦除行为相等。此外，补偿电压可以施加到NAND串的一个或多个选择栅极，以补偿耦合到来自选择栅极的一个或多个存储器单元的电压。可以使用各种补偿电压。

10. 发明申请

WO2011008367A1 DYNAMICALLY ADJUSTABLE ERASE AND PROGRAM LEVELS FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的动态可调删除和程序级别
公开(公告)号：WO2011008367A1
公开(公告)日：2011-01-20
申请号：PCT/US2010/037845
申请日：2010-06-08
申请人： SANDISK CORPORATION , DONG, Yingda , WAN, Jun
发明人： DONG, Yingda , WAN, Jun
IPC分类号： G11C16/16 , G11C16/34
CPC分类号： G11C16/344 , G11C16/16
摘要： Degradation of non-volatile storage elements is reduced by adaptively adjusting erase-verify levels and program-verify levels. The number of erase pulses, (1) or the highest erase pulse amplitude, needed to complete an erase operation is determined. When the number, or amplitude, reaches a limit (2), the erase-verify level is increased (3). As the erase-verify level is increased, the number of required erase pulses decreases since the erase operation can be completed more easily. An accelerating increase in the degradation is thus avoided. One or more program- verify levels can also be increased in concert with changes in the erase-verify level. The one or more program- verify levels can increase by the same increment as the erase-verify level to maintain a constant threshold voltage window between the erased state and a programmed state, or by a different increment. Implementations with binary or multi-level storage elements are provided. (1) =1124,1132), (2) = 1136). (3)1138)
摘要翻译：通过自适应地调整擦除验证级别和程序验证级别来降低非易失性存储元件的降级。确定完成擦除操作所需的擦除脉冲数（1）或最高擦除脉冲幅度。当数字或幅度达到极限（2）时，擦除验证电平增加（3）。随着擦除验证电平的增加，所需擦除脉冲的数量减少，因为擦除操作可以更容易地完成。从而避免了退化的加速增加。一个或多个程序验证电平也可以随着擦除验证电平的变化而增加。一个或多个程序验证电平可以增加与擦除验证电平相同的增量，以在擦除状态和编程状态之间维持恒定的阈值电压窗口，或者通过不同的增量。提供了具有二进制或多级存储元素的实现。（1）= 1124,1132）（2）= 1136）。（3）1138）

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