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1. 发明申请

WO2007008903A3 MEMORY CELL COMPRISING A THIN FILM THREE-TERMINAL SWITCHING DEVICE HAVING A METAL SOURCE AND/OR DRAIN REGION 审中-公开
标题翻译：包含金属源和/或排水区域的薄膜三端开关装置的存储单元
公开(公告)号：WO2007008903A3
公开(公告)日：2007-06-21
申请号：PCT/US2006026898
申请日：2006-07-11
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , PETTI CHRISTOPHER J
发明人： SCHEUERLEIN ROY E , PETTI CHRISTOPHER J
IPC分类号： H01L21/8247 , G11C11/34 , G11C11/56 , G11C13/02 , G11C16/02 , H01L21/84 , H01L27/06 , H01L27/07 , H01L27/112 , H01L27/115 , H01L27/12 , H01L27/24
CPC分类号： H01L27/1203 , G11C11/5614 , G11C11/5685 , G11C13/0007 , G11C13/0011 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L21/84 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L27/115 , H01L27/11502 , H01L27/11507 , H01L27/2436 , H01L27/2454 , H01L29/685 , H01L29/786 , H01L29/8605 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/1675
摘要： A nonvolatile memory cell comprising a switchable resistor memory element ion reservoir (212) , chalcogenide (214) , silicided top electrode (216 and 202) and a thin-film three- terminal switching device, preferably a MOSFET source/drain regions (220) , channel (224) , gate dielectric (226) , gate (228) in series. The switchable resistor memory element has the property of having at least two stable resistance states, for example a high- resistance state and a low-resistance state. It is switched between the two states, and its resistance state (and thus the data state of the cell) is sensed by providing appropriate current through the three-terminal switching device . At least one source/drain region of the switching device is not formed by a doped semiconductor region but forms a schottky contact with the channel . Preferred embodiments of the present invention include a highly dense monolithic three dimensional memory array in which multiple memory levels of such memory cells are formed above a single substrate such as a monocrystalline silicon wafer.
摘要翻译：一种非易失性存储单元，包括可切换电阻器存储元件离子储存器（212），硫族化物（214），硅化顶部电极（216和202）和薄膜三端开关器件，优选MOSFET源极/漏极区域（220），通道（224），栅极电介质（226），栅极（228）。可切换电阻存储元件具有至少两个稳定的电阻状态的特性，例如高电阻状态和低电阻状态。它在两个状态之间切换，并且通过提供通过三端开关装置的适当电流来感测其电阻状态（以及因此的小区的数据状态）。开关器件的至少一个源极/漏极区域不是由掺杂半导体区域形成，而是形成与沟道的肖特基接触。本发明的优选实施例包括高密度单片三维存储器阵列，其中这种存储器单元的多个存储器级别形成在诸如单晶硅晶片的单个衬底上方。

2. 发明申请

WO2008016421A3 MIXED-USE MEMORY ARRAY WITH DIFFERENT DATA STATES AND METHOD FOR USE THEREWITH 审中-公开
标题翻译：具有不同数据状态的混合使用存储器阵列及其使用方法
公开(公告)号：WO2008016421A3
公开(公告)日：2008-05-02
申请号：PCT/US2007013772
申请日：2007-06-12
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , PETTI CHRISTOPHER J
发明人： SCHEUERLEIN ROY E , PETTI CHRISTOPHER J
IPC分类号： G11C11/56 , G11C13/02
CPC分类号： G11C17/165 , G11C11/56 , G11C11/5692 , G11C13/0002 , G11C17/16 , G11C29/76 , G11C2211/5641 , G11C2211/5646 , G11C2213/72
摘要： A mixed-use memory array with different data states and a method for use therewith are disclosed. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells, each memory cell comprising a memory element comprising a switchable resistance material configurable to one of at least three resistivity states. A first set of memory cells uses X resistivity states to represent X respective data states, and a second set of memory cells uses Y resistivity states to represent Y respective data states, wherein X?Y.
摘要翻译：公开了具有不同数据状态的混合使用存储器阵列及其使用方法。在一个优选实施例中，提供了包括多个存储器单元的存储器阵列，每个存储器单元包括存储器元件，存储器元件包括可配置为至少三个电阻率状态中的一个的可切换电阻材料。第一组存储器单元使用X电阻率状态来表示X个相应的数据状态，并且第二组存储器单元使用Y电阻率状态来表示Y个相应的数据状态，其中X≥Y。

3. 发明申请

WO2008016932A2 METHOD AND APPARATUS FOR PASSIVE ELEMENT MEMORY ARRAY INCORPORATING REVERSIBLE POLARITY WORD LINE AND BIT LINE DECODERS 审中-公开
标题翻译：包含可逆极性字线和位线解码器的被动元件存储器阵列的方法和设备
公开(公告)号：WO2008016932A2
公开(公告)日：2008-02-07
申请号：PCT/US2007074883
申请日：2007-07-31
申请人： SANDISK 3D LLC , FASOLI LUCA G , PETTI CHRISTOPHER J , SCHEUERLEIN ROY E
发明人： FASOLI LUCA G , PETTI CHRISTOPHER J , SCHEUERLEIN ROY E
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C8/08 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C17/165
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程和在一些实施例中的可重写无源元件存储器单元的示例性存储器阵列的电路和方法，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。另外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择选定阵列块内的一个或多个字线和位线，用于向选定阵列块内的选定存储器单元传送数据信息并且用于将未选择的偏置条件传送给未选择的阵列块。

4. 发明申请

WO2011056534A2 METHODS OF FORMING PILLARS FOR MEMORY CELLS USING SEQUENTIAL SIDEWALL PATTERNING 审中-公开
标题翻译：使用顺序侧壁图案形成记忆细胞的柱子的方法
公开(公告)号：WO2011056534A2
公开(公告)日：2011-05-12
申请号：PCT/US2010054027
申请日：2010-10-26
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , PETTI CHRISTOPHER J , TANAKA YOICHIRO
发明人： SCHEUERLEIN ROY E , PETTI CHRISTOPHER J , TANAKA YOICHIRO
IPC分类号： H01L21/033
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention includes forming first features from a first template layer disposed above a memory layer stack; forming first sidewall spacers adjacent the first features; forming second features that extend in a first direction in a mask layer by using the first sidewall spacers as a hardmask; depositing a second template layer on the mask layer; forming third features from the second template layer; forming second sidewall spacers adjacent the third features; and forming fourth features that extend in a second direction in the mask layer by using the second sidewall spacers as a hardmask. Numerous additional aspects are disclosed.
摘要翻译：本发明提供了用于制造存储器结构的设备，方法和系统，其使用顺序侧壁图案化来形成存储器单元的柱。本发明包括从布置在存储层堆叠之上的第一模板层形成第一特征; 形成邻近所述第一部件的第一侧壁间隔物; 通过使用所述第一侧壁间隔物作为硬掩模形成在掩模层中沿第一方向延伸的第二特征; 在掩模层上沉积第二模板层; 从第二模板层形成第三特征; 形成与第三特征相邻的第二侧壁间隔物; 以及通过使用第二侧壁间隔物作为硬掩模，形成在掩模层中沿第二方向延伸的第四特征。披露了许多其他方面。

5. 发明申请

WO2008016950A3 METHOD AND APPARATUS FOR MEMORY ARRAY INCORPORATING TWO DATA BUSSES FOR MEMORY ARRAY BLOCK SELECTION 审中-公开
标题翻译：用于存储阵列选择的两个数据总线的存储器阵列的方法和装置
公开(公告)号：WO2008016950A3
公开(公告)日：2008-05-02
申请号：PCT/US2007074903
申请日：2007-07-31
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , FASOLI LUCA G , PETTI CHRISTOPHER J
发明人： SCHEUERLEIN ROY E , FASOLI LUCA G , PETTI CHRISTOPHER J
IPC分类号： G11C7/10 , G11C8/10 , G11C8/12
CPC分类号： G11C17/18 , G11C5/063 , G11C8/08 , G11C8/10 , G11C8/12 , G11C8/14
摘要： Circuits and methods (370) are described for decoding exemplary memory arrays (374, 375) of programmable, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods (370) are described for selecting one or more array blocks (374, 375) of such a memory array, for selecting one or more word lines (377) and bit lines within selected array blocks (374, 375), for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselecte array blocks.
摘要翻译：描述了用于解码可编程可重写无源元件存储单元的示例性存储器阵列（374,375）的电路和方法（370），其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。另外，描述了用于选择这种存储器阵列的一个或多个阵列块（374,375）的电路和方法（370），用于选择一个或多个字线（377）和选定阵列块（374,375）内的位线），用于将数据信息传送到所选择的阵列块内的所选择的存储器单元，以及用于传送未选择的偏置条件以取消选择阵列块。

6. 发明申请

WO2011056527A3 METHODS AND APPARATUS FOR LAYOUT OF THREE DIMENSIONAL MATRIX ARRAY MEMORY FOR REDUCED COST PATTERNING 审中-公开
标题翻译：用于降低成本花纹的三维矩阵阵列存储器的布局方法和装置
公开(公告)号：WO2011056527A3
公开(公告)日：2011-12-08
申请号：PCT/US2010054013
申请日：2010-10-26
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , PETTI CHRISTOPHER J , TANAKA YOICHIRO
发明人： SCHEUERLEIN ROY E , PETTI CHRISTOPHER J , TANAKA YOICHIRO
IPC分类号： H01L27/02 , H01L21/033 , H01L27/06 , H01L27/10
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.
摘要翻译：本发明提供了一种用于三维存储器的存储器层布局的装置，方法和系统。存储层包括多个存储器阵列块; 耦合到所述存储器阵列块的多个存储器线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。存储器线从存储器阵列块延伸并且使用侧壁限定的工艺形成。存储线具有小于用于形成存储器线的光刻工具的标称最小特征尺寸能力的半间距尺寸。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。存储线被布置成适于允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供其它存储器线路之间的区域的图案。公开了许多附加方面。

7. 发明申请

WO2006130800A2 REWRITEABLE MEMORY CELL COMPRISING A TRANSISTOR AND RESISTANCE-SWITCHING MATERIAL IN SERIES 审中-公开
标题翻译：系列中包含晶体管和电阻切换材料的可记忆存储器单元
公开(公告)号：WO2006130800A2
公开(公告)日：2006-12-07
申请号：PCT/US2006021372
申请日：2006-06-01
申请人： SANDISK 3D LLC , PETTI CHRISTOPHER J , SCHEUERLEIN ROY E
发明人： PETTI CHRISTOPHER J , SCHEUERLEIN ROY E
IPC分类号： H01L27/00 , H01L45/00
CPC分类号： H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1675
摘要： A nonvolatile memory cell is provided, the cell comprising a transistor in series with resistance- switching material, which can be switched between at least two stable resistance states, for example a high-resistance state and a low-resistance state. In preferred embodiments the transistor is a TFT, having a channel region not formed in a monocrystalline wafer substrate. In preferred embodiments the transistor may have' either a vertically oriented ch'annel or a laterally oriented channel. Either embodiment can be formed in a monolithic three dimensional memory array in which multiple memory levels can be formed above a single substrate, forming a highly dense nonvolatile memory array.
摘要翻译：提供了一种非易失性存储单元，该单元包括与电阻切换材料串联的晶体管，该晶体管可以在至少两个稳定的电阻状态之间切换，例如高电阻状态和低电阻状态。在优选实施例中，晶体管是TFT，其具有未形成在单晶晶片衬底中的沟道区。在优选实施例中，晶体管可以具有“垂直定向的ch”通道或横向定向的通道。任何一个实施例可以形成在单片三维存储器阵列中，其中可以在单个衬底上方形成多个存储器级，形成高密度非易失性存储器阵列。

8. 发明申请

WO2006107409A3 DECODING CIRCUIT FOR NON-BINARY GROUPS OF MEMORY LINE DRIVERS 审中-公开
标题翻译：解码存储线驱动器非二进制组的电路
公开(公告)号：WO2006107409A3
公开(公告)日：2007-04-19
申请号：PCT/US2006005067
申请日：2006-02-14
申请人： SANDISK , SCHEUERLEIN ROY E , PETTI CHRISTOPHER J , FASOLI LUCA G
发明人： SCHEUERLEIN ROY E , PETTI CHRISTOPHER J , FASOLI LUCA G
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C5/063 , G11C8/08 , G11C8/14
摘要： A decoding circuit for non-binary groups of memory line drivers is disclosed. In one embodiment, an integrated circuit is disclosed comprising a binary decoder and circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder. In another embodiment, an integrated circuit is disclosed comprising a memory array comprising a plurality of array lines, a non-integral-power-of-two number of array line driver circuits, and control circuitry configured to select one of the array line driver circuits. The control circuitry can comprise a binary decoder and a pre-decoder portion that performs a non-binary arithmetic operation. The concepts described herein may be used alone or in combination.
摘要翻译：公开了一种用于非二进制组的存储器线驱动器的解码电路。在一个实施例中，公开了一种集成电路，其包括二进制解码器和用于执行非二进制算术运算的电路，其中非二进制算术运算的结果被提供作为二进制解码器的输入。在另一个实施例中，公开了一种集成电路，其包括存储器阵列，该存储器阵列包括多个阵列线，两个非整数倍数的阵列线驱动器电路，以及控制电路，被配置为选择阵列线驱动电路之一。控制电路可以包括执行非二进制算术运算的二进制解码器和预解码器部分。本文所述的概念可以单独使用或组合使用。

9. 发明申请

WO2010080437A3 MEMORY CELL COMPRISING A DIODE CONNECTED TO AT LEAST THREE RESISTIVITY-SWITCHING ELEMENTS AND METHODS OF FABRICATING AND READING THE SAME 审中-公开
标题翻译：包含连接到至少三个电阻开关元件的二极管的存储单元及其制造和读取方法
公开(公告)号：WO2010080437A3
公开(公告)日：2010-09-02
申请号：PCT/US2009068234
申请日：2009-12-16
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E
发明人： SCHEUERLEIN ROY E
IPC分类号： H01L27/02 , G11C13/02 , G11C16/02 , G11C17/16 , H01L27/06 , H01L27/102 , H01L27/24 , H01L27/28 , H01L29/861
CPC分类号： H01L27/1021 , G11C13/0002 , G11C2213/72 , H01L27/0207 , H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L27/2481 , H01L29/1606 , H01L29/861 , H01L29/868
摘要： A non-volatile memory device (100) includes a first electrode (110), a diode steering element (120) at least three resistivity switching storage elements (131,132,133) and a second electrode (151) The diode steering element electrically contacts the first electrode and the at least three resistivity switching storage elements. The second electrode electrically contacts only one of the at least three resistivity switching storage elements.
摘要翻译：非易失性存储器件（100）包括第一电极（110），至少三个电阻率切换存储元件（131,132,133）和第二电极（151）的二极管操纵元件（120）。二极管操作元件电接触第一电极和至少三个电阻率切换存储元件。第二电极只电连接至少三个电阻率开关存储元件中的一个。

10. 发明申请

WO2007008902A3 NONVOLATILE MEMORY CELL COMPRISING SWITCHABLE RESISTOR AND TRANSISTOR 审中-公开
标题翻译：包含可切换电阻器和晶体管的非易失性存储器单元
公开(公告)号：WO2007008902A3
公开(公告)日：2007-09-07
申请号：PCT/US2006026897
申请日：2006-07-11
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E
发明人： SCHEUERLEIN ROY E
IPC分类号： H01L27/24
CPC分类号： H01L45/1233 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C2213/31 , G11C2213/33 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/085 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1641 , H01L45/1675
摘要： A rewriteable nonvolatile memory cell is taught comprising a thin film transistor and a switchable resistor memory element in series. The switchable resistor element decreases resistance when subjected to a set voltage magnitude applied in a first direction, and increases resistance when subjected to a reset voltage magnitude applied in a second direction opposite the first. In preferred embodiments the memory cell is formed in an array, preferably a monolithic three dimensional memory array in which multiple memory levels are formed above a single substrate. In preferred embodiments a thin film transistor and a switchable resistor memory element are electrically disposed between a data line and a reference line which are parallel. Preferably a select line extending perpendicular to the data line and reference line controls the transistor.
摘要翻译：教导了一种可重写的非易失性存储器单元，其包括串联的薄膜晶体管和可切换电阻器存储器元件。当受到在第一方向上施加的设定电压大小时，可切换电阻器元件降低电阻，并且在受到在与第一方向相反的第二方向上施加的复位电压大小时增加电阻。在优选实施例中，存储器单元形成为阵列，优选为单片三维存储器阵列，其中多个存储器级形成在单个衬底上方。在优选实施例中，薄膜晶体管和可切换电阻器存储元件电气地设置在数据线和平行的参考线之间。优选地，垂直于数据线和参考线延伸的选择线控制晶体管。

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