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1. 发明申请

WO2012044433A1 DECODER CIRCUITRY PROVIDING FORWARD AND REVERSE MODES OF MEMORY ARRAY OPERATION AND METHOD FOR BIASING SAME 审中-公开
标题翻译：提供存储器阵列操作的前向和反向模式的解码器电路及其偏移方法
公开(公告)号：WO2012044433A1
公开(公告)日：2012-04-05
申请号：PCT/US2011/050012
申请日：2011-08-31
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy E. , FASOLI, Luca G.
发明人： SCHEUERLEIN, Roy E. , FASOLI, Luca G.
IPC分类号： G11C7/18 , G11C8/08 , G11C8/12
CPC分类号： G11C7/18 , G11C7/1048 , G11C8/08 , G11C8/12 , G11C8/14
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks. The decoder circuit is operated at a relatively low voltage until its outputs are stable. Then, the operating voltage is increased and bus lines of array line drivers are pulsed.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用的可重写无源元件存储单元。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。解码器电路在相对较低的电压下工作，直到其输出稳定。然后，工作电压增加，阵列线路驱动器的总线被脉冲。

2. 发明申请

WO2009158673A1 SIMULTANEOUS WRITE AND VERIFY IN A NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储中同时写入和验证
公开(公告)号：WO2009158673A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048951
申请日：2009-06-26
申请人： SANDISK 3D LLC , FASOLI, Luca, G. , YAN, Tianhong , LEE, Jeffrey Koon, Yee
发明人： FASOLI, Luca, G. , YAN, Tianhong , LEE, Jeffrey Koon, Yee
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C16/3481 , G11C2013/0066 , G11C2213/32 , G11C2213/72
摘要： A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and resetting of the reversible resistance-switching elements.
摘要翻译：存储器系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储单元的三维存储器阵列（衬底上方），以及用于检测可逆电阻的设置和复位的电路开关元件

3. 发明申请

WO2008016946A3 METHOD AND APPARATUS FOR READING A MULTI-LEVEL PASSIVE ELEMENT MEMORY CELL ARRAY 审中-公开
标题翻译：用于读取多级被动元件存储单元阵列的方法和装置
公开(公告)号：WO2008016946A3
公开(公告)日：2009-01-08
申请号：PCT/US2007074899
申请日：2007-07-31
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , THORP TYLER J , FASOLI LUCA G
发明人： SCHEUERLEIN ROY E , THORP TYLER J , FASOLI LUCA G
IPC分类号： G11C16/04
CPC分类号： G11C11/56 , G11C11/5642 , G11C13/004 , G11C13/0069 , G11C16/24 , G11C16/26 , G11C2013/0054 , G11C2013/009 , G11C2211/5634 , G11C2213/77
摘要： A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10. The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current is sensed for at least two different combinations of reference current level and read bias voltage. A mid-level reference is used to read the LSB. When reading the MSB, a first reference between the 10 and 00 data states, and a second reference between 01 and 11 data states may be used, and the mid-level reference need not be used. In certain embodiments, the bit line current may be simultaneously compared against the first and second references, without requiring a delay to stabilize the bit line current to a different value, and the MSB generated accordingly.
摘要翻译：四级无源元件单元具有对应于降低电阻电平的存储器状态，其优选地分别映射到数据状态11,01,00和10. LSB和MSB优选地被映射为不同页面的一部分。为了区分存储单元状态，对于参考电流电平和读取偏置电压的至少两种不同的组合来检测所选择的位线电流。中间级参考用于读取LSB。当读取MSB时，可以使用10和00数据状态之间的第一个参考，并且可以使用01和11数据状态之间的第二个参考，并且不需要使用中间级参考。在某些实施例中，位线电流可以同时与第一和第二参考值进行比较，而不需要延迟来将位线电流稳定到不同的值，并且相应地生成MSB。

4. 发明申请

WO2008051835A1 MEMORY DEVICE AND METHOD FOR PROTECTING MEMORY CELLS DURING PROGRAMMING 审中-公开
标题翻译：用于在编程期间保护记忆细胞的存储器件和方法
公开(公告)号：WO2008051835A1
公开(公告)日：2008-05-02
申请号：PCT/US2007/081916
申请日：2007-10-19
申请人： SANDISK CORPORATION , FASOLI, Luca, G. , THORP, Tyler
发明人： FASOLI, Luca, G. , THORP, Tyler
IPC分类号： G11C16/10
CPC分类号： G11C11/5685 , G11C11/5678 , G11C13/0004 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C16/3481 , G11C17/18 , G11C2211/5624 , G11C2213/32
摘要： Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when programming of the memory cells has been achieved. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card.
摘要翻译：公开了用于编程存储器件的存储器单元的改进的电路和方法。改进的电路和方法用于保护存储器单元免受在编程存储器单元期间可能施加的潜在的有害电能。此外，改进的电路和方法操作以检测何时已经实现了存储器单元的编程。改进的电路和方法对于非易失性存储器单元的编程特别有用。在一个实施例中，存储器件涉及半导体存储器产品，例如半导体存储器芯片或便携式存储卡。

5. 发明申请

WO2008016950A2 METHOD AND APPARATUS FOR MEMORY ARRAY INCORPORATING TWO DATA BUSSES FOR MEMORY ARRAY BLOCK SELECTION 审中-公开
标题翻译：用于存储阵列选择的两个数据总线的存储器阵列的方法和装置
公开(公告)号：WO2008016950A2
公开(公告)日：2008-02-07
申请号：PCT/US2007/074903
申请日：2007-07-31
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , FASOLI, Luca, G. , PETTI, Christopher, J.
发明人： SCHEUERLEIN, Roy, E. , FASOLI, Luca, G. , PETTI, Christopher, J.
IPC分类号： G11C16/04
CPC分类号： G11C17/18 , G11C5/063 , G11C8/08 , G11C8/10 , G11C8/12 , G11C8/14
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

6. 发明申请

WO2004090905A2 THREE-DIMENSIONAL MEMORY DEVICE INCORPORATING SEGMENTED BIT LINE MEMORY ARRAY 审中-公开
标题翻译：配有SEGMENTED位线记忆阵列的三维存储器件
公开(公告)号：WO2004090905A2
公开(公告)日：2004-10-21
申请号：PCT/US2004/009756
申请日：2004-03-31
申请人： MATRIX SEMICONDUCTOR, INC. , SCHEUERLEIN, Roy, E. , ILKBAHAR, Alper , FASOLI, Luca, G.
发明人： SCHEUERLEIN, Roy, E. , ILKBAHAR, Alper , FASOLI, Luca, G.
IPC分类号： G11C7/18
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/0466 , G11C17/12 , G11C17/18 , G11C2213/71 , G11C2213/77 , Y10S257/91
摘要： A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line.
摘要翻译：三维（3D）高密度存储器阵列包括多个分段位线（即感测线），其中存储器阵列内的段切换器件将段连接到全局位线。分段交换设备驻留在集成电路的一个或多个层上，优选地驻留在每个位线层上。全局位线优选地位于存储器阵列下方的一个层上，但可驻留在多于一个层上。位线段优选地共享到相关联的全局位线的垂直连接。

7. 发明申请

WO2008016948A3 DUAL DATA-DEPENDENT BUSSES FOR COUPLING READ/WRITE CIRCUITS TO A MEMORY ARRAY 审中-公开
标题翻译：用于将读/写电路耦合到存储阵列的双数据相关总线
公开(公告)号：WO2008016948A3
公开(公告)日：2009-01-08
申请号：PCT/US2007074901
申请日：2007-07-31
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , FASOLI LUCA G
发明人： SCHEUERLEIN ROY E , FASOLI LUCA G
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C8/12 , G11C7/1048 , G11C7/18 , G11C8/08
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

8. 发明申请

WO2008016951A2 METHOD AND APPARATUS FOR HIERARCHICAL BIT LINE BIAS BUS FOR BLOCK SELECTABLE MEMORY ARRAY 审中-公开
标题翻译：用于块选择存储器阵列的分层位线偏置总线的方法和装置
公开(公告)号：WO2008016951A2
公开(公告)日：2008-02-07
申请号：PCT/US2007/074904
申请日：2007-07-31
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy E. , FASOLI, Luca G.
发明人： SCHEUERLEIN, Roy E. , FASOLI, Luca G.
IPC分类号： G11C16/10
CPC分类号： G11C17/16 , G11C7/1048 , G11C7/12 , G11C7/18 , G11C8/12 , G11C13/0026 , G11C13/02 , G11C17/18 , G11C2207/002 , G11C2213/71
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

9. 发明申请

WO2008016946A2 METHOD AND APPARATUS FOR READING A MULTI-LEVEL PASSIVE ELEMENT MEMORY CELL ARRAY 审中-公开
标题翻译：用于读取多级被动元件存储单元阵列的方法和装置
公开(公告)号：WO2008016946A2
公开(公告)日：2008-02-07
申请号：PCT/US2007/074899
申请日：2007-07-31
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy E. , THORP, Tyler J. , FASOLI, Luca G.
发明人： SCHEUERLEIN, Roy E. , THORP, Tyler J. , FASOLI, Luca G.
IPC分类号： G11C16/04
CPC分类号： G11C11/56 , G11C11/5642 , G11C13/004 , G11C13/0069 , G11C16/24 , G11C16/26 , G11C2013/0054 , G11C2013/009 , G11C2211/5634 , G11C2213/77
摘要： A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10. The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current is sensed for at least two different combinations of reference current level and read bias voltage. A mid-level reference is used to read the LSB. When reading the MSB, a first reference between the 10 and 00 data states, and a second reference between 01 and 11 data states may be used, and the mid-level reference need not be used. In certain embodiments, the bit line current may be simultaneously compared against the first and second references, without requiring a delay to stabilize the bit line current to a different value, and the MSB generated accordingly.
摘要翻译：四级无源元件单元具有对应于降低电阻电平的存储器状态，其优选地分别映射到数据状态11,01,00和10. LSB和MSB优选地被映射为不同页面的一部分。为了区分存储单元状态，对于参考电流电平和读取偏置电压的至少两种不同的组合来检测所选择的位线电流。中间级参考用于读取LSB。当读取MSB时，可以使用10和00数据状态之间的第一个参考，并且可以使用01和11数据状态之间的第二个参考，并且不需要使用中间级参考。在某些实施例中，位线电流可以同时与第一和第二参考值进行比较，而不需要延迟来将位线电流稳定到不同的值，并且相应地生成MSB。

10. 发明申请

WO2006107409A3 DECODING CIRCUIT FOR NON-BINARY GROUPS OF MEMORY LINE DRIVERS 审中-公开
标题翻译：解码存储线驱动器非二进制组的电路
公开(公告)号：WO2006107409A3
公开(公告)日：2007-04-19
申请号：PCT/US2006005067
申请日：2006-02-14
申请人： SANDISK , SCHEUERLEIN ROY E , PETTI CHRISTOPHER J , FASOLI LUCA G
发明人： SCHEUERLEIN ROY E , PETTI CHRISTOPHER J , FASOLI LUCA G
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C5/063 , G11C8/08 , G11C8/14
摘要： A decoding circuit for non-binary groups of memory line drivers is disclosed. In one embodiment, an integrated circuit is disclosed comprising a binary decoder and circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder. In another embodiment, an integrated circuit is disclosed comprising a memory array comprising a plurality of array lines, a non-integral-power-of-two number of array line driver circuits, and control circuitry configured to select one of the array line driver circuits. The control circuitry can comprise a binary decoder and a pre-decoder portion that performs a non-binary arithmetic operation. The concepts described herein may be used alone or in combination.
摘要翻译：公开了一种用于非二进制组的存储器线驱动器的解码电路。在一个实施例中，公开了一种集成电路，其包括二进制解码器和用于执行非二进制算术运算的电路，其中非二进制算术运算的结果被提供作为二进制解码器的输入。在另一个实施例中，公开了一种集成电路，其包括存储器阵列，该存储器阵列包括多个阵列线，两个非整数倍数的阵列线驱动器电路，以及控制电路，被配置为选择阵列线驱动电路之一。控制电路可以包括执行非二进制算术运算的二进制解码器和预解码器部分。本文所述的概念可以单独使用或组合使用。

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