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1. 发明申请

WO2011159583A4 COMPOSITION OF MEMORY CELL WITH RESISTANCE-SWITCHING LAYERS 审中-公开
标题翻译：具有电阻切换层的存储器单元的组成
公开(公告)号：WO2011159583A4
公开(公告)日：2012-08-02
申请号：PCT/US2011040105
申请日：2011-06-10
申请人： SANDISK 3D LLC , KREUPL FRANZ , BANDYOPADHYAY ABHIJIT , CHEN YUNG-TIN , FU CHU-CHEN , JAYASEKARA WIPUL PEMSIRI , KAI JAMES , MAKALA RAGHUVEER S , RABKIN PETER , SAMACHISA GEORGE , ZHANG JINGYAN
发明人： KREUPL FRANZ , BANDYOPADHYAY ABHIJIT , CHEN YUNG-TIN , FU CHU-CHEN , JAYASEKARA WIPUL PEMSIRI , KAI JAMES , MAKALA RAGHUVEER S , RABKIN PETER , SAMACHISA GEORGE , ZHANG JINGYAN
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/2409 , G11C11/16 , G11C11/1659 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
摘要翻译：三维读写存储器中的存储器件包括存储器单元。每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧具有第一和第二电阻转换层，并且在RSME的任一端具有第一和第二电极。第一和第二电阻切换层都可以具有双极性或单极性切换特性。在存储器单元的置位或复位操作中，离子电流在电阻切换层中流动，从而有助于切换机制。由于导电中间层的散射，对开关机构没有贡献的电子流被减少，以避免损坏导向元件。提供了用于RSME的不同层的特定材料和材料的组合。

2. 发明申请

WO2011159583A3 COMPOSITION OF MEMORY CELL WITH RESISTANCE-SWITCHING LAYERS 审中-公开
标题翻译：具有电阻切换层的记忆体组成
公开(公告)号：WO2011159583A3
公开(公告)日：2012-06-14
申请号：PCT/US2011040105
申请日：2011-06-10
申请人： SANDISK 3D LLC , KREUPL FRANZ , BANDYOPADHYAY ABHIJIT , CHEN YUNG-TIN , FU CHU-CHEN , JAYASEKARA WIPUL PEMSIRI , KAI JAMES , MAKALA RAGHUVEER S , RABKIN PETER , SAMACHISA GEORGE , ZHANG JINGYAN
发明人： KREUPL FRANZ , BANDYOPADHYAY ABHIJIT , CHEN YUNG-TIN , FU CHU-CHEN , JAYASEKARA WIPUL PEMSIRI , KAI JAMES , MAKALA RAGHUVEER S , RABKIN PETER , SAMACHISA GEORGE , ZHANG JINGYAN
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/2409 , G11C11/16 , G11C11/1659 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。第一和第二电阻切换层都可以具有双极或单极开关特性。在存储单元的置位或复位操作中，离子电流在电阻切换层中流动，有助于切换机构。由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。提供了用于RSME不同层的材料和材料的组合。

3. 发明申请

WO2011156343A3 NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS AND READ/WRITE CIRCUITS AND METHOD THEREOF 审中-公开
标题翻译：具有读取/写入元件的3D阵列的非易失性存储器及其读取/写入电路及其方法
公开(公告)号：WO2011156343A3
公开(公告)日：2012-03-29
申请号：PCT/US2011039405
申请日：2011-06-07
申请人： SANDISK 3D LLC , SAMACHISA GEORGE , FASOLI LUCA , LI YAN , YAN TIANHONG
发明人： SAMACHISA GEORGE , FASOLI LUCA , LI YAN , YAN TIANHONG
IPC分类号： G11C11/16 , G11C13/02
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/004 , G11C13/0097 , G11C16/06 , G11C2013/0054 , G11C2213/32 , G11C2213/71 , G11C2213/77 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/1675
摘要： A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.
摘要翻译：三维阵列特别适合于响应于在其上施加电压差而可逆地改变电导水平的存储器元件。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件连接到的位线的二维阵列从衬底垂直定向并穿过多个平面。在感测期间，为了补偿字线电阻，读出放大器在对字线的给定位置处的存储元件的感测期间参考存储的参考值。提供了在两个存储器阵列之间具有一行读出放大器的布局以便于参考。当在预定条件下经受偏置电压时，选择的存储元件被复位而不重置相邻的存储元件。

4. 发明申请

WO2010117911A2 THREE-DIMENSIONAL ARRAY OF RE-PROGRAMMABLE NON-VOLATILE MEMORY ELEMENTS HAVING VERTICAL BIT LINES 审中-公开
标题翻译：具有垂直位线的可重新编程的非易失性存储器元件的三维阵列
公开(公告)号：WO2010117911A2
公开(公告)日：2010-10-14
申请号：PCT/US2010029852
申请日：2010-04-02
申请人： SANDISK 3D LLC , SAMACHISA GEORGE
发明人： SAMACHISA GEORGE
IPC分类号： G11C11/56 , G11C13/00 , G11C13/02 , G11C16/02 , H01L27/24 , H01L45/00
CPC分类号： G11C13/003 , B82Y10/00 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C13/025 , G11C2213/19 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/78 , H01L27/2436 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/149
摘要： A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
摘要翻译：特别适用于响应于在其上施加电压差而可逆地改变电导水平的存储元件的三维阵列。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件所连接的位线从衬底垂直定向并穿过多个平面。

5. 发明申请

WO2012068127A3 TRANSISTOR DRIVEN 3D MEMORY 审中-公开
标题翻译：晶体管驱动3D存储器
公开(公告)号：WO2012068127A3
公开(公告)日：2012-07-26
申请号：PCT/US2011060812
申请日：2011-11-15
申请人： SANDISK 3D LLC , MIHNEA ANDREI , SAMACHISA GEORGE
发明人： MIHNEA ANDREI , SAMACHISA GEORGE
IPC分类号： G11C13/00 , H01L45/00
CPC分类号： G11C13/003 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C2013/0073 , G11C2213/79 , H01L27/2454 , H01L27/2463
摘要： A nonvolatile memory device with a first conductor extending in a first direction and a semiconductor element above the first conductor. The semiconductor element includes a source, a drain and a channel of a field effect transistor (JFET or MOSFET). The nonvolatile memory device also includes a second conductor above the semiconductor element, the second conductor extending in a second direction. The nonvolatile memory device also includes a resistivity switching material disposed between the first conductor and the semiconductor element or between the second conductor and the semiconductor element. The JFET or MOSFET includes a gate adjacent to the channel, and the MOSFET gate being self-aligned with the first conductor.
摘要翻译：一种具有沿第一方向延伸的第一导体和在第一导体上方的半导体元件的非易失性存储器件。半导体元件包括场效应晶体管（JFET或MOSFET）的源极，漏极和沟道。非易失性存储器件还包括在半导体元件上方的第二导体，第二导体沿第二方向延伸。非易失性存储器件还包括设置在第一导体和半导体元件之间或第二导体与半导体元件之间的电阻率切换材料。 JFET或MOSFET包括与沟道相邻的栅极，并且MOSFET栅极与第一导体自对准。

6. 发明申请

WO2008008630A3 HIGHLY DENSE MONOLITHIC THREE DIMENSIONAL MEMORY ARRAY AND METHOD FOR FORMING 审中-公开
标题翻译：高密度单片三维存储阵列和形成方法
公开(公告)号：WO2008008630A3
公开(公告)日：2008-04-03
申请号：PCT/US2007072301
申请日：2007-06-28
申请人： SANDISK 3D LLC , YUAN JACK , SAMACHISA GEORGE
发明人： YUAN JACK , SAMACHISA GEORGE
IPC分类号： H01L27/102 , H01L27/06 , H01L27/24
CPC分类号： H01L27/1021 , H01L27/24
摘要： A method to form a highly dense monolithic three dimensional memory array is provided. In preferred embodiments, conductive or semiconductor spacers (116) can be formed, then used as hard masks to pattern underlying layer in a self -aligned manner, forming features at sublithographic pitch. Methods of the invention minimize photomasking steps and thus simplify fabrication. The method is used for forming crosspoint memory arrays comprising fuses, antif uses or chalcogenide switching elements. Several memory layers are stacked one on top of the other.
摘要翻译：提供了形成高密度单片三维存储器阵列的方法。在优选实施例中，可以形成导电或半导体间隔物（116），然后用作硬掩模以自对准方式图案化下层，以亚光刻间距形成特征。本发明的方法使光掩模步骤最小化，从而简化制造。该方法用于形成包括熔丝，反用途或硫族化物开关元件的交叉点存储器阵列。几个内存层堆叠在另一个之上。

7. 发明申请

WO2012003301A3 ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：超高密度垂直NAND存储器件及其制造方法
公开(公告)号：WO2012003301A3
公开(公告)日：2012-04-19
申请号：PCT/US2011042566
申请日：2011-06-30
申请人： SANDISK TECHNOLOGIES INC , ALSMEIER JOHANN , PURAYATH VINOD , CHIEN HENRY , MATAMIS GEORGE , LEE YAO-SHENG , KAI JAMES , ZHANG YUAN , SAMACHISA GEORGE
发明人： ALSMEIER JOHANN , PURAYATH VINOD , CHIEN HENRY , MATAMIS GEORGE , LEE YAO-SHENG , KAI JAMES , ZHANG YUAN , SAMACHISA GEORGE
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66833 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/66825 , H01L29/78642 , H01L29/7889 , H01L29/7926
摘要： Monolithic, three dimensional NAND strings and manufacturing methods are disclosed. The channel (1) of the strings can be vertical or V-shaped. The core the channel can be filled with an insulator. The control gates ( 3 ) are recessed with respect to intermediate dielectric layers. The charge storage regions ( 9 ) and the blocking dielectric (7) are formed in the recesses. Shielding wings (12) can be formed next to the control gates.
摘要翻译：公开了单片三维NAND串和制造方法。弦的通道（1）可以是垂直的或V形的。通道的芯可以填充绝缘体。控制栅极（3）相对于中间介电层凹陷。电荷存储区（9）和阻挡电介质（7）形成在凹部中。屏蔽翼（12）可以在控制门旁边形成。

8. 发明申请

WO2013192216A3 MEMORIES WITH CYLINDRICAL READ/WRITE STACKS 审中-公开
标题翻译：具有圆柱读/写堆栈的记忆
公开(公告)号：WO2013192216A3
公开(公告)日：2014-03-20
申请号：PCT/US2013046379
申请日：2013-06-18
申请人： SANDISK 3D LLC
发明人： CHIEN HENRY , LEE YAO-SHENG , SAMACHISA GEORGE , ALSMEIER JOHANN
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： B42D15/02 , A63F13/00 , G11C5/02 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C2213/71 , H01L21/82 , H01L27/2409 , H01L27/2454 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1273 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1616
摘要： A three-dimensional memory is formed as an array of memory elements across multiple layers positioned at different distances above a semiconductor substrate. Cylindrical stacks of memory elements are formed where a cylindrical opening has read/write material deposited along its wall, and a cylindrical vertical bit line formed along its central axis. Memory elements formed on either side of such a cylinder may include sheet electrodes that extend into the read/write material.
摘要翻译：三维存储器形成为跨越位于半导体衬底上方不同距离的多个层的存储元件的阵列。形成存储元件的圆柱形堆叠，其中圆柱形开口具有沿其壁沉积的读/写材料，以及沿其中心轴线形成的圆柱形垂直位线。形成在这种气缸两侧的记忆元件可以包括延伸到读/写材料中的片电极。

9. 发明申请

WO2007121343A3 METHODS OF MAKING FLASH MEMORY CELL ARRAYS HAVING DUAL CONTROL GATES PER MEMORY CELL CHARGE STORAGE ELEMENT 审中-公开
标题翻译：每个存储单元充电存储元件制作具有双重控制门的闪存存储单元阵列的方法
公开(公告)号：WO2007121343A3
公开(公告)日：2007-12-21
申请号：PCT/US2007066610
申请日：2007-04-13
申请人： SANDISK CORP , HARARI ELIYAHOU , SAMACHISA GEORGE
发明人： HARARI ELIYAHOU , SAMACHISA GEORGE
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L29/42336
摘要： Methods of fabricating a dual control gate non-volatile memory array are described. Parallel strips (1705) of floating gate material are formed over the substrate (1700) in a first direction but separated from it by a tunnel dielectric (1702). In the gaps between these strips control gate material (1735) is forming a second set of parallel strips but insulated from both the adjacent floating gate stripes and the substrate. Both sets of strips are isolated in a second direction perpendicular to the first direction forming an array of individual floating gates and control gates. The control gates formed from an individual control gate strip are then interconnected by a conductive wordline (1735) such that the potential on individual floating gates is controlled by the voltages on two adjacent wordlines. In other variations either the floating gates or the control gates may be recessed into the original substrate.
摘要翻译：描述了制造双重控制门非易失性存储器阵列的方法。浮动栅极材料的平行条（1705）在第一方向上形成在衬底（1700）上方，但是由隧道电介质（1702）与其隔开。在这些条带之间的间隙中，控制栅极材料（1735）正在形成第二组平行条带，但与相邻的浮栅条和基板两者绝缘。两组条带在垂直于第一方向的第二方向上被隔离，形成单独的浮动栅极和控制栅极的阵列。然后，由单独的控制栅极条形成的控制栅极通过导电字线（1735）互连，使得各个浮动栅极上的电位由两个相邻字线上的电压控制。在其他变型中，浮动栅极或控制栅极可以凹入原始衬底。

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