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1. 发明申请

WO2011084334A3 CARBON/TUNNELING-BARRIER/CARBON DIODE 审中-公开
公开(公告)号：WO2011084334A3
公开(公告)日：2011-07-14
申请号：PCT/US2010/059555
申请日：2010-12-08
申请人： SANDISK 3D LLC , BANDYOPADHYAY, Abhijit , KREUPL, Franz , MIHNEA, Andrei , LI, Xiao
发明人： BANDYOPADHYAY, Abhijit , KREUPL, Franz , MIHNEA, Andrei , LI, Xiao
IPC分类号： H01L45/00
摘要： A carbon/tunneling-barrier/carbon diode and method for forming the same are disclosed. The carbon/tunneling-barrier/carbon may be used as a steering element in a memory array. Each memory cell in the memory array may include a reversible resistivity-switching element and a carbon/tunneling- barrier/carbon diode as the steering element. The tunneling-barrier may include a semiconductor or an insulator. Thus, the diode may be a carbon/semiconductor/carbon diode. The semiconductor in the diode may be intrinsic or doped. The semiconductor may be depleted when the diode is under equilibrium conditions. For example, the semiconductor may be lightly doped such that the depletion region extends from one end of the semiconductor region to the other end. The diode may be a carbon/insulator/carbon diode.

2. 发明申请

WO2013141904A1 RRAM CELL WITH A RESISTANCE SWITCHING MATERIAL BEING A LOCAL PROTECTIVE RESISTOR 审中-公开
标题翻译：具有电阻切换材料的RRAM电池是本地保护电阻
公开(公告)号：WO2013141904A1
公开(公告)日：2013-09-26
申请号：PCT/US2012/066912
申请日：2012-11-28
申请人： SANDISK 3D LLC , XIAO, Li , GORLA, Chandu , BANDYOPADHYAY, Abhijit , MIHNEA, Andrei
发明人： XIAO, Li , GORLA, Chandu , BANDYOPADHYAY, Abhijit , MIHNEA, Andrei
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C5/02 , G11C8/10 , G11C13/0023 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2013/0083 , G11C2213/32 , G11C2213/33 , G11C2213/71 , G11C2213/72 , G11C2213/76 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： A memory cell in a 3-D read and write memory device has two bipolar resistance-switching layers with different respective switching currents. A low current resistance-switching layer can be switched in set and reset processes while a high current resistance-switching layer remains in a reset state and acts as a protection resistor to prevent excessively high currents on the low current resistance-switching layer. The low and high current resistance-switching layers can be of the same material such as a metal oxide, where the layers differ in terms of thickness, doping, leakiness, metal richness or other variables. Or, the low and high current resistance-switching layers can be of different materials, having one or more layers each. The high current resistance- switching layer can have a switching current which is greater than a switching current of the low current resistance-switching layer by a factor of at least 1.5 or 2.0, for instance.
摘要翻译： 3-D读写存储器件中的存储单元具有两个具有不同开关电流的双极性电阻切换层。低电流电阻切换层可以在置位和复位过程中被切换，而高电流电阻切换层保持复位状态，并且作为保护电阻来防止低电流电阻切换层上的过大电流。低电流和高电流电阻切换层可以是相同的材料，例如金属氧化物，其中层的厚度，掺杂，泄漏，金属浓度等变化不同。或者，低电流和高电流电阻切换层可以是不同的材料，每个具有一个或多个层。例如，高电流电阻切换层可以具有比低电流电阻切换层的开关电流大至少1.5或2.0的开关电流。

3. 发明申请

WO2012068127A2 TRANSISTOR DRIVEN 3D MEMORY 审中-公开
公开(公告)号：WO2012068127A2
公开(公告)日：2012-05-24
申请号：PCT/US2011/060812
申请日：2011-11-15
申请人： SANDISK 3D LLC , MIHNEA, Andrei , SAMACHISA, George
发明人： MIHNEA, Andrei , SAMACHISA, George
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C2013/0073 , G11C2213/79 , H01L27/2454 , H01L27/2463
摘要： A nonvolatile memory device with a first conductor extending in a first direction and a semiconductor element above the first conductor. The semiconductor element includes a source, a drain and a channel of a field effect transistor (JFET or MOSFET). The nonvolatile memory device also includes a second conductor above the semiconductor element, the second conductor extending in a second direction. The nonvolatile memory device also includes a resistivity switching material disposed between the first conductor and the semiconductor element or between the second conductor and the semiconductor element. The JFET or MOSFET includes a gate adjacent to the channel, and the MOSFET gate being self-aligned with the first conductor.
摘要翻译：具有在第一方向上延伸的第一导体和在第一导体上方的半导体元件的非易失性存储器件。半导体元件包括场效应晶体管（JFET或MOSFET）的源极，漏极和沟道。非易失性存储器件还包括在半导体元件上方的第二导体，第二导体沿第二方向延伸。非易失性存储器件还包括布置在第一导体和半导体元件之间或者第二导体和半导体元件之间的电阻率切换材料。 JFET或MOSFET包括与沟道相邻的栅极，并且MOSFET栅极与第一导体自对准。

4. 发明申请

WO2012051041A1 MULTI-LEVEL MEMORY ARRAYS WITH MEMORY CELLS THAT EMPLOY BIPOLAR STORAGE ELEMENTS AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：具有使用双极存储元件的存储器单元的多级存储器阵列及其形成方法
公开(公告)号：WO2012051041A1
公开(公告)日：2012-04-19
申请号：PCT/US2011/055076
申请日：2011-10-06
申请人： SANDISK 3D, LLC , CHEN, Yung-Tin , MIHNEA, Andrei , SCHEUERLEIN, Roy E. , FASOLI, Luca
发明人： CHEN, Yung-Tin , MIHNEA, Andrei , SCHEUERLEIN, Roy E. , FASOLI, Luca
IPC分类号： H01L27/24 , H01L45/00 , G11C13/00
CPC分类号： H01L27/2481 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： A memory array is provided that includes a first memory cell (200-1) having a first conductive line (202a); a first bipolar storage element (102-1) formed above the first conductive line; and a second conductive line (302) formed above the first bipolar storage element; and a second memory cell (200-2) formed above the first memory cell and having a second bipolar storage element (102-2) formed above the second conductive line; and a third conductive line (202b) formed above the second bipolar storage element. The first and second memory cells share the second conductive line (302); the first bipolar storage element (102-1) has a first storage element polarity orientation within the first memory cell; the second bipolar storage element (102-2) has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation.
摘要翻译：提供一种存储器阵列，其包括具有第一导线（202a）的第一存储单元（200-1）; 形成在第一导线上方的第一双极存储元件（102-1）; 和形成在所述第一双极存储元件上方的第二导线（302）; 以及形成在所述第一存储单元上方并具有形成在所述第二导线上方的第二双极存储元件（102-2）的第二存储单元（200-2）以及形成在所述第二双极存储元件上方的第三导线（202b）。第一和第二存储单元共享第二导线（302）; 第一双极存储元件（102-1）在第一存储单元内具有第一存储元件极性取向; 第二双极存储元件（102-2）在第二存储单元内具有第二存储元件极性取向; 并且第二存储元件极性取向与第一存储元件极性取向相反。

5. 发明申请

WO2011049907A1 PUNCH-THROUGH DIODE STEERING ELEMENT 审中-公开
标题翻译： PUNCH-THROUGH二极管转向元件
公开(公告)号：WO2011049907A1
公开(公告)日：2011-04-28
申请号：PCT/US2010/053128
申请日：2010-10-19
申请人： SANDISK 3D LLC , MIHNEA, Andrei , SEKAR, Deepak, C. , SAMACHISA, George , SCHEUERLEIN, Roy , XIAO, Li
发明人： MIHNEA, Andrei , SEKAR, Deepak, C. , SAMACHISA, George , SCHEUERLEIN, Roy , XIAO, Li
IPC分类号： G11C13/00 , H01L27/24
CPC分类号： G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/32 , G11C2213/34 , G11C2213/72 , H01L27/24
摘要： A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P-/N+ device or a P+/N-/P+ device.
摘要翻译：描述了一种用于形成使用穿通二极管作为与可逆电阻率开关元件串联的转向元件的存储系统的存储系统和方法。穿通二极管允许交叉点存储器阵列的双极性操作。穿通二极管可具有对称的非线性电流/电压关系。穿通二极管在选择的电池的高偏压下具有高电流，对于未选择的电池，在低偏压下具有低泄漏电流。因此，它与具有电阻式开关元件的交叉点存储器阵列中的双极开关兼容。穿通二极管可以是N + / P- / N +器件或P + / N- / P +器件。

6. 发明申请

WO2006132903A2 NON-VOLATILE MEMORY CELLS WITHOUT DIFFUSION JUNCTIONS 审中-公开
标题翻译：非扩散记忆细胞没有扩散结
公开(公告)号：WO2006132903A2
公开(公告)日：2006-12-14
申请号：PCT/US2006/021239
申请日：2006-06-02
申请人： MICRON TECHNOLOGY, INC. , MIHNEA, Andrei , MORADI, Behnam , ARITOME, Seiichi , LI, Di
发明人： MIHNEA, Andrei , MORADI, Behnam , ARITOME, Seiichi , LI, Di
IPC分类号： H01L27/115 , H01L21/8247 , G11C16/04
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A plurality of memory cell stacks are formed over a substrate. The substrate does not have diffusion regions between each memory cell stack to link the memory cells. The cells are formed close enough such that the memory cells are linked serially by the electric fields generated by each floating gate in the channel regions. In one embodiment, an n- layer is implanted at the top of the substrate to increase conductivity between cells. The select transistors can be linked to the serial string by diffusion regions or by interaction of the electric fields between the select transistor channel and the memory cell channel.
摘要翻译：多个存储单元堆叠形成在衬底上。衬底在每个存储单元堆之间不具有扩散区，以连接存储单元。电池形成得足够接近，使得存储器单元由通道区域中的每个浮动栅极产生的电场串联连接。在一个实施例中，在衬底的顶部注入n层以增加电池之间的导电性。选择晶体管可以通过扩散区域或通过选择晶体管沟道和存储单元通道之间的电场的相互作用而连接到串行串。

7. 发明申请

WO2009002871A1 FLOATING GATE FLASH CELL 审中-公开
标题翻译：浮动门闪存单元
公开(公告)号：WO2009002871A1
公开(公告)日：2008-12-31
申请号：PCT/US2008/067744
申请日：2008-06-20
申请人： MICRON TECHNOLOGY, INC. , MIHNEA, Andrei
发明人： MIHNEA, Andrei
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： Memory cells, memory arrays, memory devices and methods are disclosed, such as those involving a memory cell comprising a floating gate comprising lightly doped polysilicon, wherein the lightly doped polysilicon has a substantially uniform doping concentration. One such memory cell further comprises a control gate and dielectric disposed between the floating gate and the control gate.
摘要翻译：公开了存储器单元，存储器阵列，存储器件和方法，例如涉及包括包含轻掺杂多晶硅的浮置栅极的存储单元的那些，其中轻掺杂多晶硅具有基本均匀的掺杂浓度。一个这样的存储单元还包括设置在浮置栅极和控制栅极之间的控制栅极和电介质。

8. 发明申请

WO2014074408A2 3D STACKED NON-VOLATILE STORAGE PROGRAMMING TO CONDUCTIVE STATE 审中-公开
标题翻译： 3D堆叠非易失性存储编程到导电状态
公开(公告)号：WO2014074408A2
公开(公告)日：2014-05-15
申请号：PCT/US2013/068041
申请日：2013-11-01
申请人： SANDISK TECHNOLOGIES, INC. , MIHNEA, Andrei , COSTA, Xiying , ZHANG, Yanli
发明人： MIHNEA, Andrei , COSTA, Xiying , ZHANG, Yanli
IPC分类号： G11C11/56 , G11C16/10 , H01L27/115
CPC分类号： G11C11/5671 , G11C16/0483 , G11C16/10 , H01L27/1157 , H01L27/11582
摘要： Programming NAND strings in a 3D stacked storage device to a conductive state is disclosed. Storage elements may be erased by raising their Vt and programmed by lowering their Vt. Programming may include applying a series of increasing voltages to selected bit lines until the selected memory cell is programmed. Unselected bit lines may be held at about ground, or close to ground. The selected word line may be grounded, or be held close to ground. Unselected word lines between the selected word line and the bit line may receive about the selected bit line voltage. Unselected word lines between the source line and the selected word line may receive about half the selected bit line voltage. Programming may be achieved without boosting channels of unselected NAND strings to inhibit them from programming. Therefore, program disturb associated with leakage of boosted channel potential may be avoided.
摘要翻译：公开了将3D堆叠存储设备中的NAND串编程为导通状态。存储元件可以通过升高Vt并通过降低Vt进行编程而被擦除。编程可能包括对选定的位线施加一系列增加的电压，直到选定的存储单元被编程为止。未选择的位线可以保持在大约地面或靠近地面。所选择的字线可以接地，或者靠近地面。所选择的字线和位线之间的未被选择的字线可以接收所选位线电压。源极线和所选字线之间的未选字线可以接收大约一半的选定位线电压。可以在不增加未选择的NAND串的通道以阻止它们编程的情况下实现编程。因此，可以避免与提升的通道电位的泄漏相关的程序干扰。

9. 发明申请

WO2006012292A1 MINIMIZING ADJACENT WORDLINE DISTURB IN A MEMORY DEVICE 审中-公开
标题翻译：在存储器件中最小化相邻字符干扰
公开(公告)号：WO2006012292A1
公开(公告)日：2006-02-02
申请号：PCT/US2005/022469
申请日：2005-06-24
申请人： MICRON TECHNOLOGY, INC. , RUDECK, Paul, J. , MIHNEA, Andrei , BICKSLER, Andrew
发明人： RUDECK, Paul, J. , MIHNEA, Andrei , BICKSLER, Andrew
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized V Pass disturb in response to the selected wordline programming voltage.
摘要翻译：耦合到用于编程的单元的所选字线被编程电压偏置。与所选字线相邻的未选字线被偏置在第一预定电压。剩余的字线被偏置在大于第一预定电压的第二预定电压。通过确定哪些未选择的相邻字线偏置电压产生最小化的V

10. 发明公开

EP2641248A2 TRANSISTOR DRIVEN 3D MEMORY 失效转让
标题翻译： TRANSISTORGESTEUERTER 3D-SPEICHER
公开(公告)号：EP2641248A2
公开(公告)日：2013-09-25
申请号：EP11785883.7
申请日：2011-11-15
申请人： Sandisk 3d, Llc
发明人： MIHNEA, Andrei , SAMACHISA, George
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C2013/0073 , G11C2213/79 , H01L27/2454 , H01L27/2463
摘要： A nonvolatile memory device with a first conductor extending in a first direction and a semiconductor element above the first conductor. The semiconductor element includes a source, a drain and a channel of a field effect transistor (JFET or MOSFET). The nonvolatile memory device also includes a second conductor above the semiconductor element, the second conductor extending in a second direction. The nonvolatile memory device also includes a resistivity switching material disposed between the first conductor and the semiconductor element or between the second conductor and the semiconductor element. The JFET or MOSFET includes a gate adjacent to the channel, and the MOSFET gate being self-aligned with the first conductor.
摘要翻译：一种具有沿第一方向延伸的第一导体和在第一导体上方的半导体元件的非易失性存储器件。半导体元件包括场效应晶体管（JFET或MOSFET）的源极，漏极和沟道。非易失性存储器件还包括在半导体元件上方的第二导体，第二导体沿第二方向延伸。非易失性存储器件还包括设置在第一导体和半导体元件之间或第二导体与半导体元件之间的电阻率切换材料。 JFET或MOSFET包括与沟道相邻的栅极，MOSFET栅极与第一导体自对准。

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