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1. 发明申请

WO2003102780A1 METHOD AND APPARATUS FOR MULTITHREADED CACHE WITH CACHE EVICTION BASED ON THREAD IDENTIFIER 审中-公开
标题翻译：基于螺纹识别器的多速缓存高速缓存的方法和设备
公开(公告)号：WO2003102780A1
公开(公告)日：2003-12-11
申请号：PCT/US2003/017332
申请日：2003-06-03
申请人： SANDBRIDGE TECHNOLOGIES, INC.
发明人： HOKENEK, Erdem , GLOSSNER, John, C. , HOANE, Arthur, Joseph , MOUDGILL, Mayan , WANG, Shenghong
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , G06F12/0842 , G06F12/128
摘要： A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches (400’) each implementing a thread-based eviction process that reduces the amount of replacement policy storage required in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array (402) having multiple sets (set 1-set 4) of memory locations, and a directory (404) for storing tags (404-k) each corresponding to at least a portion of a particular address of one of the memory locations. The directory (404) has multiple entries each storing multiple ones of the tags (404-k), such that if there are n sets of memory locations in the memory array, there are n tags (404-k) associated with each directory entry. The directory (404) is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array. An entry in a particular one of the memory locations is selected for eviction from the given thread cache in conjunction with a cache miss event, based at least in part on at least a portion of a thread identifier of the given thread cache.
摘要翻译：用于多线程处理器的高速缓存存储器包括多个设置关联线程高速缓冲存储器，其中一个或多个线程高速缓冲存储器（400'）各自实现基于线程的逐出过程，该过程减少了在高速缓存存储器。在说明性实施例中的至少一个线程高速缓存中的给定的一个包括具有存储器位置的多个集合（集合1集合4）的存储器阵列（402）和用于存储每个对应的标签（404-k）的目录（404）到存储器位置之一的特定地址的至少一部分。目录（404）具有多个条目，每个条目存储多个标签（404-k），使得如果存储器阵列中存在n组存储器位置，则存在与每个目录条目相关联的n个标签（404-k）。目录（404）被用于实现访问请求和存储器阵列的存储器位置之间的集合关联地址映射。至少部分地基于给定线程高速缓存的线程标识符的至少一部分，选择存储器位置中的特定一个存储器位置中的入口与给定的线程高速缓存结合高速缓存未命中事件进行驱逐。

2. 发明申请

WO2009114691A2 METHOD FOR ACHIEVING POWER SAVINGS BY DISABLING A VALID ARRAY 审中-公开
标题翻译：通过禁用有效阵列实现节电的方法
公开(公告)号：WO2009114691A2
公开(公告)日：2009-09-17
申请号：PCT/US2009/036958
申请日：2009-03-12
申请人： SANDBRIDGE TECHNOLOGIES, INC. , HOANE, Arthur, Joseph
发明人： HOANE, Arthur, Joseph
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0802 , G06F12/0891 , G06F2212/1028 , Y02D10/13
摘要： A method is described for use when a cache is accessed. Before all valid array entries are validated, a valid array entry is read when a data array entry is accessed. If the valid array entry is a first array value, access to the cache is treated as being invalid and the data array entry is reloaded. If the valid array entry is a second array value, a tag array entry is compared with an address to determine if the data array entry is valid or invalid. A valid control register contains a first control value before all valid array entries are validated and a second control value after all valid array entries are validated. After the second control value is established, reads of the valid array are disabled and the tag array entry is compared with the address to determine if a data array entry is valid or invalid.
摘要翻译：描述了一种用于访问高速缓存时使用的方法。在所有有效的数组条目都被验证之前，访问数据数组条目时会读取一个有效的数组条目。如果有效数组条目是第一个数组值，则对高速缓存的访问将被视为无效，并重新加载数据数组条目。如果有效数组条目是第二个数组值，则将标记数组条目与地址进行比较以确定数据数组条目是有效还是无效。一个有效的控制寄存器包含一个第一个控制值，在所有的有效数组条目被验证之前和在所有有效的数组条目被验证之后的第二个控制值。第二个控制值建立后，禁止读取有效数组，并将标记数组条目与地址进行比较，以确定数据数组条目是有效还是无效。

3. 发明公开

EP1532532A1 METHOD AND APPARATUS FOR MULTITHREADED CACHE WITH CACHE EVICTION BASED ON THREAD IDENTIFIER 审中-公开
标题翻译：方法和装置基于线程标识符与缓存缓存放电的多线程
公开(公告)号：EP1532532A1
公开(公告)日：2005-05-25
申请号：EP03756358.2
申请日：2003-06-03
申请人： Sandbridge Technologies, Inc.
发明人： HOKENEK, Erdem , GLOSSNER, John, C. , HOANE, Arthur, Joseph , MOUDGILL, Mayan , WANG, Shenghong
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , G06F12/0842 , G06F12/128
摘要： A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches (400’) each implementing a thread-based eviction process that reduces the amount of replacement policy storage required in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array (402) having multiple sets (set 1-set 4) of memory locations, and a directory (404) for storing tags (404-k) each corresponding to at least a portion of a particular address of one of the memory locations. The directory (404) has multiple entries each storing multiple ones of the tags (404-k), such that if there are n sets of memory locations in the memory array, there are n tags (404-k) associated with each directory entry. The directory (404) is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array. An entry in a particular one of the memory locations is selected for eviction from the given thread cache in conjunction with a cache miss event, based at least in part on at least a portion of a thread identifier of the given thread cache.

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