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1. 发明授权

KR100870567B1 A METHOD OF PLASMA ION DOPING PROCESS AND AN APPARATUS THEREOF 无效
标题翻译：等离子体掺杂方法及其装置的方法
公开(公告)号：KR100870567B1
公开(公告)日：2008-11-27
申请号：KR20070063805
申请日：2007-06-27
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： HONG SOO JIN , CHOI SI YOUNG , PARK TAI SU , LEE JIN WOOK , KANG JONG HOON , KIM MI JIN
IPC分类号： H01L21/265 , H01L21/205
CPC分类号： H01L21/2236 , H01J37/32412 , H01J37/32449
摘要： A plasma ion-doping method is provided to prevent a deterioration of the performance of the semiconductor device generated by ion doping. The plasma ion-doping method is provided. The wafer(30) is introduced on the susceptor(20) within the reaction chamber(10). The ion doping source gas(40) is injected from the upper part of the reaction chamber to mask plasma. The control gas(50) is supplied from the lower part of the reaction chamber. The ions are doped in the wafer. The ion doping gas is a halide gas. The control gas is a deposition gas. The deposition gas is a silane based gas. The diluent gas is an inert gas including at least one of He, Ne, Ar, Xe. The control gas is flown in the horizontal direction to the surface of wafer. The lower part gas injecting holes are formed around the susceptor.
摘要翻译：提供等离子体离子掺杂方法以防止由离子掺杂产生的半导体器件的性能的劣化。提供等离子体离子掺杂方法。将晶片（30）引入反应室（10）内的基座（20）上。离子掺杂源气体（40）从反应室的上部注入以对等离子体进行掩模。控制气体（50）从反应室的下部供给。离子掺杂在晶片中。离子掺杂气体是卤化物气体。控制气体是沉积气体。沉积气体是硅烷基气体。稀释气体是包括He，Ne，Ar，Xe中的至少一种的惰性气体。控制气体在水平方向上流向晶片表面。下部气体注入孔形成在基座周围。

2. 发明公开

KR20070107336A METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：KR20070107336A
公开(公告)日：2007-11-07
申请号：KR20060039679
申请日：2006-05-02
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： PARK JIN HO , NAM BYEONG YUN , NAM JEONG LIM , JANG SOO LK , LEE SI HYUNG , LEE SANG HYEOP , LEE JOON JAE , KIM CHAN WON , KANG PIL KYU , JEON KYUNG YUB , KIM MI JIN
IPC分类号： H01L21/336
摘要： A method for manufacturing a semiconductor device is provided to restrict increase of electric potential within active pins which do not relate electrically by an electric field generated by gate patterns. A plurality of active pins(115a) arranged into two dimension are formed on a substrate, having a extended length toward a first direction(x). An isolation layer(120) filling a gap between the active pins are formed. Trenches having a line shape is formed to expose sidewalls of the active pins adjacent to active pins parallel to the first direction by etching partially the isolation layer, at this time protrusion parts are formed between the active pins according to the first direction. Gate patterns are formed to fill the trenches with a predetermined interval, cross the top portion of the protrusion parts and the active pins toward a second direction.
摘要翻译：提供一种制造半导体器件的方法，以限制由栅极图案产生的电场而不与电气相关的有源引脚内的电位增加。在基板上形成多个排列成二维的活动销（115a），其长度朝向第一方向（x）延伸。形成填充有源销之间的间隙的隔离层（120）。形成具有线状的沟槽形成为通过部分地蚀刻隔离层而露出与主动销相邻的活动销的侧壁平行于第一方向，此时根据第一方向在活动销之间形成突出部分。形成栅极图形以以预定间隔填充沟槽，跨越突出部分的顶部部分和活动销向第二方向。

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