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1. 发明申请

US20050146918A1 Semiconductor device having semiconductor memory with sense amplifier 有权
公开(公告)号：US20050146918A1
公开(公告)日：2005-07-07
申请号：US11059569
申请日：2005-02-17
申请人： Ryu Ogiwara , Daisaburo Takashima , Michael Jacob
发明人： Ryu Ogiwara , Daisaburo Takashima , Michael Jacob
IPC分类号： G11C7/06 , G11C11/22
CPC分类号： G11C7/04 , G11C7/062 , G11C7/067 , G11C11/22
摘要： A semiconductor device comprises a memory cell array, bit line, /bit line complementary to the bit line, reference voltage generating circuit and sense amplifier. The bit line is connected to the memory cells and applied with a voltage read from each memory cell of the memory cell array. The /bit line is supplied with a reference voltage. The reference voltage generating circuit generates the reference voltage that has temperature dependence for compensating a change in the voltage, read to the bit line, due to temperature. The reference voltage generating circuit controls the reference voltage such that the reference voltage assumes a midpoint of trails of a signal value distribution indicative of “0” data and a signal value distribution indicative of “1” data. The sense amplifier compares the voltage, read to the bit line, with the reference voltage supplied to the /bit line, and amplifies the difference therebetween.

2. 发明授权

US06898104B2 Semiconductor device having semiconductor memory with sense amplifier 失效
标题翻译：具有读出放大器的半导体存储器的半导体器件
公开(公告)号：US06898104B2
公开(公告)日：2005-05-24
申请号：US10291610
申请日：2002-11-12
申请人： Ryu Ogiwara , Daisaburo Takashima , Michael Jacob
发明人： Ryu Ogiwara , Daisaburo Takashima , Michael Jacob
IPC分类号： G11C7/06 , G11C11/22
CPC分类号： G11C7/04 , G11C7/062 , G11C7/067 , G11C11/22
摘要： A semiconductor device comprises a memory cell array, bit line, /bit line complementary to the bit line, reference voltage generating circuit and sense amplifier. The bit line is connected to the memory cells and applied with a voltage read from each memory cell of the memory cell array. The /bit line is supplied with a reference voltage. The reference voltage generating circuit generates the reference voltage that has temperature dependence for compensating a change in the voltage, read to the bit line, due to temperature. The reference voltage generating circuit controls the reference voltage such that the reference voltage assumes a midpoint of trails of a signal value distribution indicative of “0” data and a signal value distribution indicative of “1” data. The sense amplifier compares the voltage, read to the bit line, with the reference voltage supplied to the /bit line, and amplifies the difference therebetween.
摘要翻译：半导体器件包括存储单元阵列，与位线互补的位线/ /位线，参考电压产生电路和读出放大器。位线连接到存储器单元并且被施加从存储单元阵列的每个存储单元读取的电压。 /位线提供参考电压。参考电压产生电路产生具有温度依赖性的参考电压，用于补偿由温度读取到位线的电压变化。参考电压产生电路控制参考电压，使得参考电压采取指示“0”数据的信号值分布的轨迹的中点和指示“1”数据的信号值分布。读出放大器将读取到位线的电压与提供给/位线的参考电压进行比较，并放大它们之间的差值。

3. 发明授权

US07142473B2 Semiconductor device having semiconductor memory with sense amplifier 有权
标题翻译：具有读出放大器的半导体存储器的半导体器件
公开(公告)号：US07142473B2
公开(公告)日：2006-11-28
申请号：US11059569
申请日：2005-02-17
申请人： Ryu Ogiwara , Daisaburo Takashima , Michael Jacob
发明人： Ryu Ogiwara , Daisaburo Takashima , Michael Jacob
IPC分类号： G11C7/04
CPC分类号： G11C7/04 , G11C7/062 , G11C7/067 , G11C11/22
摘要： A semiconductor device comprises a memory cell array, bit line, /bit line complementary to the bit line, reference voltage generating circuit and sense amplifier. The bit line is connected to the memory cells and applied with a voltage read from each memory cell of the memory cell array. The /bit line is supplied with a reference voltage. The reference voltage generating circuit generates the reference voltage that has temperature dependence for compensating a change in the voltage, read to the bit line, due to temperature. The reference voltage generating circuit controls the reference voltage such that the reference voltage assumes a midpoint of trails of a signal value distribution indicative of “0” data and a signal value distribution indicative of “1” data. The sense amplifier compares the voltage, read to the bit line, with the reference voltage supplied to the /bit line, and amplifies the difference therebetween.
摘要翻译：半导体器件包括存储单元阵列，与位线互补的位线/ /位线，参考电压产生电路和读出放大器。位线连接到存储器单元并且被施加从存储单元阵列的每个存储单元读取的电压。 /位线提供参考电压。参考电压产生电路产生具有温度依赖性的参考电压，用于补偿由温度读取到位线的电压变化。参考电压产生电路控制参考电压，使得参考电压采取指示“0”数据的信号值分布的轨迹的中点和指示“1”数据的信号值分布。读出放大器将读取到位线的电压与提供给/位线的参考电压进行比较，并放大它们之间的差值。

4. 发明授权

US08159285B2 Current supply circuit 有权
标题翻译：电流供应电路
公开(公告)号：US08159285B2
公开(公告)日：2012-04-17
申请号：US12729169
申请日：2010-03-22
申请人： Takeshi Hioka , Ryu Ogiwara , Daisaburo Takashima
发明人： Takeshi Hioka , Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G05F1/10
CPC分类号： G05F1/561
摘要： A current supply circuit according to an embodiment of the present invention includes an operational amplifier having first and second input terminals and an output terminal, a transistor having a control terminal connected to the output terminal of the operational amplifier, and having first and second main terminals, a first resistance arranged between the first input terminal of the operational amplifier and the first main terminal of the transistor, a second resistance arranged between a predetermined node and a ground line, the predetermined node being between the first input terminal of the operational amplifier and the first resistance, first to Nth transistors, each of which has a control terminal connected to the control terminal or the second main terminal of the transistor, and has a main terminal outputting a current, where N is an integer of two or larger, and first to Nth switching transistors, each of which has a main terminal, the main terminals of the first to Nth switching transistors being respectively connected to the main terminals of the first to Nth transistors, a pulse width of a signal provided to a control terminal of the respective first to Nth switching transistors being set to be constant regardless of a pulse frequency of the signal.
摘要翻译：根据本发明的实施例的电流供应电路包括具有第一和第二输入端和输出端的运算放大器，具有连接到运算放大器的输出端的控制端的晶体管，并具有第一和第二主端布置在运算放大器的第一输入端和晶体管的第一主端之间的第一电阻，布置在预定节点和地线之间的第二电阻，所述预定节点位于运算放大器的第一输入端和第一电阻，第一至第N晶体管，每个具有连接到晶体管的控制端子或第二主端子的控制端子，并且具有输出电流的主端子，其中N为2或更大的整数，以及第一至第N开关晶体管，其中每个具有主端子，主端子为第一至第N开关正弦晶体管分别连接到第一至第N晶体管的主端子，提供给相应的第一至第N开关晶体管的控制端的信号的脉冲宽度被设置为恒定，而与信号的脉冲频率无关。

5. 发明授权

US07816976B2 Power supply circuit using insulated-gate field-effect transistors 有权
标题翻译：使用绝缘栅场效应晶体管的电源电路
公开(公告)号：US07816976B2
公开(公告)日：2010-10-19
申请号：US12250999
申请日：2008-10-14
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A power supply circuit is disclosed. The power supply circuit is provided with a reference voltage generation circuit to receive a voltage from a higher voltage supply so as to generate a reference voltage. The reference voltage from the reference voltage generation circuit is outputted to a power supply voltage generation circuit. The power supply voltage generation circuit boosts the reference voltage to generate a boosted power supply voltage. The boosted power supply voltage is inputted to a bandgap reference circuit. The bandgap reference circuit generates a reference voltage by using the boosted power supply voltage.
摘要翻译：公开了电源电路。电源电路设置有用于接收来自较高电压源的电压以产生参考电压的参考电压产生电路。来自参考电压产生电路的参考电压被输出到电源电压产生电路。电源电压产生电路提升参考电压以产生升高的电源电压。升压的电源电压被输入到带隙基准电路。带隙参考电路通过使用升压电源电压产生参考电压。

6. 发明授权

US07633330B2 Reference voltage generation circuit 失效
标题翻译：参考电压发生电路
公开(公告)号：US07633330B2
公开(公告)日：2009-12-15
申请号：US11934970
申请日：2007-11-05
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： According to an aspect of the present invention, there is provided a reference voltage generation circuit including: a first transistor having a first gate, a first source and a first drain; a second transistor having a second gate connected to the first gate, a second source connected to the first source and a second drain; a first diode connected between a ground and a V− node; a first resistor connected between the V− node and the first drain; a second diode and a second resistor connected between the ground and a V+ node; a third resistor connected between the V+ node and the first drain; an operational amplifier including input ports connected to the V+ node and the V− node and an output port connected to the first gate and the second gate; and a fourth resistor connected between the ground and the second drain.
摘要翻译：根据本发明的一个方面，提供了一种参考电压产生电路，包括：具有第一栅极，第一源极和第一漏极的第一晶体管; 第二晶体管，具有连接到第一栅极的第二栅极，连接到第一源极和第二漏极的第二源极; 连接在地和V节点之间的第一二极管; 连接在V节点和第一漏极之间的第一电阻器; 连接在地和V +节点之间的第二二极管和第二电阻器; 连接在V +节点和第一漏极之间的第三电阻器; 运算放大器，包括连接到V +节点和V节点的输入端口以及连接到第一门极和第二门极的输出端口; 以及连接在地和第二漏极之间的第四电阻器。

7. 发明申请

US20080285327A1 Ferroelectric Memory and Semiconductor Memory 审中-公开
标题翻译：铁电存储器和半导体存储器
公开(公告)号：US20080285327A1
公开(公告)日：2008-11-20
申请号：US11934399
申请日：2007-11-02
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C11/22 , G11C11/401
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管。作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值电压和比较放大。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

8. 发明授权

US07411809B2 Ferroelectric memory to be tested by applying disturbance voltage to a plurality of ferroelectric capacitors at once in direction to weaken polarization, and method of testing the same 失效
标题翻译：通过在多个强电介质电容器上施加干扰电压以便弱化极化的方向进行测试的铁电存储器及其测试方法
公开(公告)号：US07411809B2
公开(公告)日：2008-08-12
申请号：US11417154
申请日：2006-05-04
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C11/22 , G11C5/06 , G11C7/00 , G11C29/00
CPC分类号： G11C11/22 , G11C11/223 , G11C29/06 , G11C29/08 , G11C29/12005 , G11C2029/1204
摘要： A unit cell is formed by a ferroelectric capacitor and first MOS transistor, and a block is formed by connecting a plurality of unit cells in series. The gates of the first MOS transistors in the individual unit cells are connected to word lines, which are selectively driven by a word line driver on the basis of a row address signal. A plate line is connected to one terminal of the block, and driven by a plate line driver. A bit line is connected to the other terminal of the block via a second MOS transistor for block selection, and selected by a column decoder on the basis of a column address. A driver/controller controls the plate line driver and column decoder to apply a potential difference between the plate line and bit line, while a plurality of word lines are kept off.
摘要翻译：单元由铁电电容器和第一MOS晶体管形成，并且通过串联连接多个单元电池而形成块。单个单元电池中的第一MOS晶体管的栅极连接到字线，该字线由字线驱动器基于行地址信号选择性地驱动。板线连接到块的一个端子，并由板线驱动器驱动。位线通过用于块选择的第二MOS晶体管连接到块的另一端，并且由列解码器基于列地址选择。驱动器/控制器控制板线驱动器和列解码器以在板线和位线之间施加电位差，同时多个字线被保持关闭。

9. 发明申请

US20050276140A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20050276140A1
公开(公告)日：2005-12-15
申请号：US10931978
申请日：2004-09-02
申请人： Ryu Ogiwara , Daisaburo Takashima , Thomas Roehr
发明人： Ryu Ogiwara , Daisaburo Takashima , Thomas Roehr
IPC分类号： G11C11/22 , G03B42/02 , G03C5/16 , G11C7/04 , G11C7/14
CPC分类号： G11C7/14 , G03B42/02 , G11C7/04 , G11C11/22
摘要： A dummy capacitor drive potential VDC is given to one electrode of a dummy capacitor, and a reference potential for determining a data value of a memory cell is generated in the other electrode thereof. A potential generator circuit for generating the potential VDC is composed of a BGR circuit outputting a potential VBGRTEMP having temperature dependency, and resistors R3 and R4, which are series-connected between an output terminal of the BGR circuit and a ground point. The potential VDC is output from a connection point of the resistors R3 and R4. Temperature dependency of the potential VDC is adjusted based on a resistance ratio of resistors R1-1, R1-2 and R2, and the absolute value is adjusted based on a resistance ratio of resistors R3 and R4.
摘要翻译：虚拟电容器驱动电位VDC被提供给虚拟电容器的一个电极，并且在其另一个电极中产生用于确定存储器单元的数据值的参考电位。用于产生电位VDC的潜在发电机电路由输出具有温度依赖性的电位VBGRTEMP的BGR电路和串联连接在BGR电路的输出端子与接地点之间的电阻器R 3和R 4构成。从电阻器R 3和R 4的连接点输出电位VDC。电阻VDC的温度依赖性根据电阻器R 1 - 1，R 1 - 2和R 2的电阻比进行调整，并且绝对值根据电阻器R 3和R 4的电阻比进行调整。

10. 发明授权

US06671200B2 Ferroelectric random access memory with isolation transistors coupled between a sense amplifier and an equalization circuit 有权
标题翻译：铁电随机存取存储器，其隔离晶体管耦合在读出放大器和均衡电路之间
公开(公告)号：US06671200B2
公开(公告)日：2003-12-30
申请号：US10372886
申请日：2003-02-26
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管，并且作为栅极电压的最小值在板线电压升高和比较放大期间获得的晶体管的晶体管小于作为板线电压下降期间获得的晶体管中的栅极电压的最大值和比较放大的值。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

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