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1. 发明授权

US08125816B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08125816B2
公开(公告)日：2012-02-28
申请号：US12488450
申请日：2009-06-19
申请人： Ryousuke Takizawa , Shinichiro Shiratake
发明人： Ryousuke Takizawa , Shinichiro Shiratake
IPC分类号： G11C11/22
CPC分类号： G11C7/12 , G11C7/22 , G11C11/22 , G11C11/4074 , G11C11/4076 , G11C11/4094 , G11C29/08
摘要： According to the present invention, a semiconductor storage device includes: a first memory cell array including: a first bit line; a first plate line; a first memory cell; a first sense amplifier; a first reference power line configured to supply first reference voltage; a first switching module configured to control a connection between the first reference power line and the first bit line; a second memory cell array including: a second bit line; a second plate line; a second memory cell; a second sense amplifier; a second reference power line configured to supply second reference voltage; a second switching module configured to control a connection between the second reference power line and the second bit line; a control module configured to generate the control signal so as to control a time difference between the first memory cell array and the second memory cell array in precharge operation.
摘要翻译：根据本发明，半导体存储装置包括：第一存储单元阵列，包括：第一位线; 第一板线第一存储单元; 第一感测放大器; 第一参考电源线，被配置为提供第一参考电压; 第一切换模块，被配置为控制所述第一参考电力线和所述第一位线之间的连接; 第二存储单元阵列，包括：第二位线; 第二板线; 第二存储单元; 第二感测放大器; 配置为提供第二参考电压的第二参考电源线; 第二切换模块，被配置为控制所述第二参考电力线和所述第二位线之间的连接; 控制模块，被配置为产生控制信号，以便在预充电操作中控制第一存储单元阵列和第二存储单元阵列之间的时间差。

2. 发明申请

US20090323390A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20090323390A1
公开(公告)日：2009-12-31
申请号：US12422083
申请日：2009-04-10
申请人： Ryousuke Takizawa , Shinichiro Shiratake
发明人： Ryousuke Takizawa , Shinichiro Shiratake
IPC分类号： G11C11/22 , G11C11/24 , G11C8/08 , G11C7/02
CPC分类号： G11C11/22 , G11C8/08
摘要： A memory includes a cell block including ferroelectric capacitors and cell transistors, the cell block being configured by unit cells formed by the ferroelectric capacitor and the cell transistor; a dummy block configured by having one end of dummy strings connected in common, the dummy string being formed by connecting in series dummy transistors; dummy word lines connected to gates of the dummy transistors; a dummy block selection transistor connected between the dummy block and a bit line; wherein in a data read operation, a dummy-word-line driver sets the dummy transistors to a conductive state, the number of the dummy transistors in the conductive state depends on the number of the cell transistors present between the unit cell to be read and the bit line, and the dummy transistors in a conductive state are conductive to the bit line.
摘要翻译：存储器包括：包括铁电电容器和单元晶体管的单元块，所述单元块由所述铁电电容器和所述单元晶体管形成的单位单元构成; 通过将虚设串的一端共同连接而构成的虚拟块，通过连接虚拟晶体管形成虚设串; 连接到虚拟晶体管的栅极的虚拟字线; 连接在虚拟块和位线之间的虚拟块选择晶体管; 其中在数据读取操作中，虚拟字线驱动器将虚拟晶体管设置为导通状态，导通状态中的虚设晶体管的数量取决于存在于要读取的单元单元之间的单元晶体管的数量和位线和导通状态的虚拟晶体管对位线是导通的。

3. 发明申请

US20090316470A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20090316470A1
公开(公告)日：2009-12-24
申请号：US12488450
申请日：2009-06-19
申请人： Ryousuke Takizawa , Shinichiro Shiratake
发明人： Ryousuke Takizawa , Shinichiro Shiratake
IPC分类号： G11C11/22 , G11C11/24 , G11C7/00 , G11C5/14
CPC分类号： G11C7/12 , G11C7/22 , G11C11/22 , G11C11/4074 , G11C11/4076 , G11C11/4094 , G11C29/08
摘要： According to the present invention, a semiconductor storage device includes: a first memory cell array including: a first bit line; a first plate line; a first memory cell; a first sense amplifier; a first reference power line configured to supply first reference voltage; a first switching module configured to control a connection between the first reference power line and the first bit line; a second memory cell array including: a second bit line; a second plate line; a second memory cell; a second sense amplifier; a second reference power line configured to supply second reference voltage; a second switching module configured to control a connection between the second reference power line and the second bit line; a control module configured to generate the control signal so as to control a time difference between the first memory cell array and the second memory cell array in precharge operation.
摘要翻译：根据本发明，半导体存储装置包括：第一存储单元阵列，包括：第一位线; 第一板线第一存储单元; 第一感测放大器; 配置为提供第一参考电压的第一参考电源线; 第一切换模块，被配置为控制所述第一参考电力线和所述第一位线之间的连接; 第二存储单元阵列，包括：第二位线; 第二板线; 第二存储单元; 第二感测放大器; 配置为提供第二参考电压的第二参考电源线; 第二切换模块，被配置为控制所述第二参考电力线和所述第二位线之间的连接; 控制模块，被配置为产生控制信号，以便在预充电操作中控制第一存储单元阵列和第二存储单元阵列之间的时间差。

4. 发明授权

US08134349B2 Power supply circuit that outputs a voltage stepped down from a power supply voltage 失效
标题翻译：输出从电源电压降压的电源的电源电路
公开(公告)号：US08134349B2
公开(公告)日：2012-03-13
申请号：US12404438
申请日：2009-03-16
申请人： Hidehiro Shiga , Shinichiro Shiratake , Daisaburo Takashima
发明人： Hidehiro Shiga , Shinichiro Shiratake , Daisaburo Takashima
IPC分类号： G05F1/613
CPC分类号： G05F1/56
摘要： A power supply circuit has a constant voltage circuit, a first MOS transistor, a second MOS transistor, a third MOS transistor, a first voltage dividing circuit that outputs a first divided voltage obtained by dividing the voltage of the output terminal by a first voltage dividing ratio, and a first differential amplifier circuit which is fed with a reference voltage and the first divided voltage and has an output connected to a gate of the second MOS transistor. The first differential amplifier circuit outputs a signal to turn on the second MOS transistor when the first divided voltage is higher than the reference voltage, and the first differential amplifier circuit outputs a signal to turn off the second MOS transistor when the first divided voltage is lower than the reference voltage.
摘要翻译：电源电路具有恒压电路，第一MOS晶体管，第二MOS晶体管，第三MOS晶体管，第一分压电路，输出通过将输出端子的电压除以第一分压而得到的第一分压以及馈送有参考电压的第一差分放大器电路和第一分压，并且具有连接到第二MOS晶体管的栅极的输出。当第一分压高于参考电压时，第一差分放大器电路输出信号以接通第二MOS晶体管，并且当第一分压电压较低时，第一差分放大器电路输出关闭第二MOS晶体管的信号比参考电压。

5. 发明授权

US08085573B2 Ferroelectric memory 有权
标题翻译：铁电存储器
公开(公告)号：US08085573B2
公开(公告)日：2011-12-27
申请号：US12562951
申请日：2009-09-18
申请人： Shinichiro Shiratake
发明人： Shinichiro Shiratake
IPC分类号： G11C11/22 , G11C7/02
CPC分类号： G11C11/22 , G11C29/808
摘要： A ferroelectric memory of an embodiment of the present invention includes a plurality of units, in each of which a ferroelectric capacitor and a transistor are connected to each other in parallel. The memory includes first and second memory cell arrays, first and second bit lines arranged in the first and second memory cell arrays, respectively, first and second blocks connected to the first bit line, and including N1 units and N2 units, respectively, where N1 and N2 are positive integers, third and fourth bit lines arranged in the first and second memory cell arrays, respectively, third and fourth blocks connected to the third bit line, and including N3 units and N4 units, respectively, where N3 and N4 are positive integers, first to fourth redundant blocks respectively connected to the first to fourth bit lines, and to be used for repair of the first to fourth blocks, and a sense amplifier selectively connectable to one of the first and second bit lines, and selectively connectable to one of the third and fourth bit lines.
摘要翻译：本发明实施例的铁电存储器包括多个单元，每个单元中的每一个中的铁电电容器和晶体管彼此并联连接。存储器包括第一和第二存储单元阵列，分别布置在第一和第二存储单元阵列中的第一和第二位线，分别连接到第一位线的第一和第二块，并且分别包括N1个单元和N2个单元，其中N1 N2是分别位于第一和第二存储单元阵列中的正整数，第三和第四位线，分别连接到第三位线的第三和第四块，并且分别包括N3单元和N4单元，其中N3和N4是正的整数，分别连接到第一至第四位线的第一至第四冗余块，并且用于修复第一至第四块;以及读出放大器，其选择性地可连接到第一和第二位线之一，并且可选择地连接到第三位和第四位之一。

6. 发明授权

US07487370B2 Semiconductor device and system 有权
标题翻译：半导体器件和系统
公开(公告)号：US07487370B2
公开(公告)日：2009-02-03
申请号：US11216018
申请日：2005-09-01
申请人： Shinichiro Shiratake , Yukihito Oowaki , Hiroyuki Hara , Tetsuya Fujita , Fumitoshi Hatori , Masataka Matsui
发明人： Shinichiro Shiratake , Yukihito Oowaki , Hiroyuki Hara , Tetsuya Fujita , Fumitoshi Hatori , Masataka Matsui
IPC分类号： G06F1/00
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： According to the present invention, there is provided a semiconductor device including a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level. The power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.
摘要翻译：根据本发明，提供了一种半导体器件，包括：电源电路，接收所提供的外部电源电压，并输出不高于外部电源电压的内部电源电压; 接收内部电源电压并执行预定操作的系统模块; 以及性能监视电路，其在施加所述内部电源电压时测量所述系统模块的处理速度，并且基于所述处理速度，输出请求将所述外部电源电压设置为第一的第一控制信号电平和第二控制信号，其请求所述电源电路将内部电源电压设定在第二电平。电源电路基于施加到其上的第二控制信号输出具有第二电平的内部电源电压。

7. 发明授权

US07352227B2 Semiconductor device having plurality of circuits belonging to different voltage domains 失效
标题翻译：具有属于不同电压域的多个电路的半导体器件
公开(公告)号：US07352227B2
公开(公告)日：2008-04-01
申请号：US11271848
申请日：2005-11-14
申请人： Shinichiro Shiratake , Hiroyuki Hara
发明人： Shinichiro Shiratake , Hiroyuki Hara
IPC分类号： H03L5/00
CPC分类号： H03K3/356113
摘要： A first inverter circuit comprises a first transistor in which one end of a current path is grounded, and a second transistor in which one end of a current path is connected to the other end of the current path of the first transistor. A first signal is supplied to gates of the first and second transistors. A third transistor is connected between the other end of the current path of the second transistor and a node to which a second voltage higher than the first voltage is supplied. A control signal constituted of one of the ground potential and the second voltage is supplied to a gate of the third transistor behind a change of a first signal. A second signal constituted of one of the ground potential and the second voltage is output from an output terminal of the first inverter circuit.
摘要翻译：第一逆变器电路包括其中电流路径的一端接地的第一晶体管和电流路径的一端连接到第一晶体管的电流通路的另一端的第二晶体管。向第一和第二晶体管的栅极提供第一信号。第三晶体管连接在第二晶体管的电流通路的另一端和高于第一电压的第二电压的节点之间。由地电位和第二电压之一组成的控制信号在第一信号的改变之后提供给第三晶体管的栅极。从第一反相器电路的输出端子输出由接地电位和第二电压之一构成的第二信号。

8. 发明授权

US07269049B2 Ferroelectric random access memory device 失效
标题翻译：铁电随机存取存储器件
公开(公告)号：US07269049B2
公开(公告)日：2007-09-11
申请号：US11046878
申请日：2005-02-01
申请人： Hidehiro Shiga , Shinichiro Shiratake , Daisaburo Takashima
发明人： Hidehiro Shiga , Shinichiro Shiratake , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C7/14
摘要： A plurality of ferroelectric memory cells is arrayed. One terminal of each memory cells arrayed in the same column is connected in common to a first bit line. A gate of a transistor of memory cells arrayed in the same row is connected in common to a word line. The other terminal of each of memory cells arrayed in the same column or the same row is connected in common to a cell plate line. A second bit line is connected with a reference voltage supply circuit. The first and second bit lines are connected with a data read circuit. The data read circuit includes a sense amplifier and a current mirror circuit having a pair of current input node connected to the first and second bit lines, and carrying the same current flowing through one of the first and second bit line to the other bit line.
摘要翻译：排列多个铁电存储单元。排列在同一列中的每个存储单元的一个端子共同连接到第一位线。排列在同一行中的存储单元的晶体管的栅极共同连接到字线。排列在同一列或同一行中的每个存储单元的另一个端子共同连接到单元格板线。第二位线与参考电压供应电路连接。第一和第二位线与数据读取电路连接。数据读取电路包括读出放大器和电流镜像电路，其具有连接到第一和第二位线的一对电流输入节点，并且将流过第一和第二位线之一的相同电流传送到另一位线。

9. 发明申请

US20060279977A1 Ferroelectric memory device having ferroelectric capacitor 失效
标题翻译：具有铁电电容器的铁电存储器件
公开(公告)号：US20060279977A1
公开(公告)日：2006-12-14
申请号：US11447940
申请日：2006-06-07
申请人： Hidehiro Shiga , Shinichiro Shiratake , Daisaburo Takashima
发明人： Hidehiro Shiga , Shinichiro Shiratake , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory device includes a cell block, a bit line, and a plate line. The cell block includes a ferroelectric capacitor and a transistor switch. The bit line applies a voltage to one electrode of the ferroelectric capacitor. The plate line applies a voltage to the other electrode of the ferroelectric capacitor. In a read operation of data, a first voltage is applied to the plate line. In a write operation of data, a second voltage different from the first voltage is applied to the plate line, and a voltage which is higher or lower than the second voltage is applied to the bit line.
摘要翻译：铁电存储器件包括电池块，位线和板线。电池块包括铁电电容器和晶体管开关。位线向铁电电容器的一个电极施加电压。板线向铁电电容器的另一个电极施加电压。在数据的读取操作中，向板线施加第一电压。在数据的写入操作中，不同于第一电压的第二电压被施加到板线，并且高于或低于第二电压的电压被施加到位线。

10. 发明申请

US20060221725A1 Semiconductor integrated circuit device 失效
公开(公告)号：US20060221725A1
公开(公告)日：2006-10-05
申请号：US11430935
申请日：2006-05-10
申请人： Kuninori Kawabata , Akira Kikutake , Shinichiro Shiratake
发明人： Kuninori Kawabata , Akira Kikutake , Shinichiro Shiratake
IPC分类号： G11C7/00
CPC分类号： G11C29/12 , G11C7/1048 , G11C11/4096
摘要： A semiconductor device includes signal lines over which signals are transferred, and a drive circuit driving the signal lines in operating modes. The operating modes include a dynamic operation mode in which the signal lines are precharged, and a static operation mode in which the signal lines are not precharged.

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