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1. 发明授权

US08625085B2 Defect evaluation method for semiconductor 有权
标题翻译：半导体缺陷评估方法
公开(公告)号：US08625085B2
公开(公告)日：2014-01-07
申请号：US13407943
申请日：2012-02-29
申请人： Ryosuke Watanabe , Masashi Tsubuku , Takayuki Inoue
发明人： Ryosuke Watanabe , Masashi Tsubuku , Takayuki Inoue
IPC分类号： G01N21/00
CPC分类号： H01L22/14 , H01L22/12
摘要： Even in the case of a sample exhibiting low photoresponse, such as a wide bandgap semiconductor, a measurement method which enables highly accurate CPM measurement is provided. When CPM measurement is performed, photoexcited carriers which are generated by light irradiation of a sample exhibiting low photoresponse such as a wide bandgap semiconductor are instantly removed by application of positive bias voltage to a third electrode which is provided in the sample in addition to two electrodes used for measurement. When the photoexcited carriers are removed, even in the case of the sample exhibiting low photoresponse, the controllability of a photocurrent value is improved and CPM measurement can be performed accurately.
摘要翻译：即使在具有低光响应的样品（例如宽带隙半导体）的情况下，也提供了能够进行高度精确的CPM测量的测量方法。当进行CPM测量时，通过向除了两个电极之外的样品中提供的第三电极施加正偏置电压，立即除去通过光照射出具有低光响应的样品（例如宽带隙半导体）产生的光激发载流子用于测量。当除去光激发载体时，即使在样品表现出较低的光响应的情况下，光电流值的可控性得到改善，也可以精确地进行CPM测量。

2. 发明授权

US08481377B2 Method for manufacturing a semiconductor device with impurity doped oxide semiconductor 有权
标题翻译：制造具有杂质掺杂氧化物半导体的半导体器件的方法
公开(公告)号：US08481377B2
公开(公告)日：2013-07-09
申请号：US13026518
申请日：2011-02-14
申请人： Kengo Akimoto , Ryosuke Watanabe , Masashi Tsubuku , Shunpei Yamazaki
发明人： Kengo Akimoto , Ryosuke Watanabe , Masashi Tsubuku , Shunpei Yamazaki
IPC分类号： H01L21/338
CPC分类号： H01L29/7869 , H01L29/41733 , H01L29/66969 , H01L29/78618
摘要： It is an object to provide a semiconductor device including an oxide semiconductor, in which miniaturization of a transistor is achieved and the concentration of an electric field is relieved. The width of a gate electrode is reduced and a space between a source electrode layer and a drain electrode layer is shortened. By adding a rare gas in a self-alignment manner with the use of a gate electrode as a mask, a low-resistance region in contact with a channel formation region can be provided in an oxide semiconductor layer. Accordingly, even when the width of the gate electrode, that is, the line width of a gate wiring is small, the low-resistance region can be provided with high positional accuracy, so that miniaturization of a transistor can be realized.
摘要翻译：本发明的目的是提供一种包括氧化物半导体的半导体器件，其中实现了晶体管的小型化和电场的集中。栅电极的宽度减小，源电极层和漏电极层之间的间隔缩短。通过使用栅电极作为掩模以自对准的方式添加稀有气体，可以在氧化物半导体层中提供与沟道形成区域接触的低电阻区域。因此，即使栅电极的宽度，即栅极配线的线宽小，也能够提供高电位区域的高位置精度，能够实现晶体管的小型化。

3. 发明授权

US08871565B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08871565B2
公开(公告)日：2014-10-28
申请号：US13222513
申请日：2011-08-31
申请人： Shunpei Yamazaki , Yusuke Nonaka , Takayuki Inoue , Masashi Tsubuku , Kengo Akimoto , Akiharu Miyanaga
发明人： Shunpei Yamazaki , Yusuke Nonaka , Takayuki Inoue , Masashi Tsubuku , Kengo Akimoto , Akiharu Miyanaga
IPC分类号： H01L21/44 , H01L29/786
CPC分类号： H01L29/78606 , H01L23/552 , H01L23/564 , H01L29/04 , H01L29/66969 , H01L29/7869 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： An object is to manufacture a semiconductor device including an oxide semiconductor film, which has stable electric characteristics and high reliability. A crystalline oxide semiconductor film is formed, without performing a plurality of steps, as follows: by utilizing a difference in atomic weight of plural kinds of atoms included in an oxide semiconductor target, zinc with low atomic weight is preferentially deposited on an oxide insulating film to form a seed crystal including zinc; and tin, indium, or the like with high atomic weight is deposited on the seed crystal while causing crystal growth. Further, a crystalline oxide semiconductor film is formed by causing crystal growth using a seed crystal with a hexagonal crystal structure including zinc as a nucleus, whereby a single crystal oxide semiconductor film or a substantially single crystal oxide semiconductor film is formed.
摘要翻译：本发明的目的是制造具有稳定的电特性和高可靠性的氧化物半导体膜的半导体装置。通过利用包含在氧化物半导体靶中的多种原子的原子量的差异，形成结晶氧化物半导体膜，而不进行多个步骤，优选将低原子量的锌沉积在氧化物绝缘膜上形成包含锌的晶种; 并且具有高原子量的锡，铟等沉积在晶种上同时引起晶体生长。此外，通过使用具有包含锌作为核的六方晶系结构的晶种进行晶体生长来形成结晶氧化物半导体膜，从而形成单晶氧化物半导体膜或大致单晶氧化物半导体膜。

4. 发明授权

US08901552B2 Top gate thin film transistor with multiple oxide semiconductor layers 有权
标题翻译：具有多个氧化物半导体层的顶栅薄膜晶体管
公开(公告)号：US08901552B2
公开(公告)日：2014-12-02
申请号：US13226713
申请日：2011-09-07
申请人： Shunpei Yamazaki , Yusuke Nonaka , Takayuki Inoue , Masashi Tsubuku , Kengo Akimoto , Akiharu Miyanaga
发明人： Shunpei Yamazaki , Yusuke Nonaka , Takayuki Inoue , Masashi Tsubuku , Kengo Akimoto , Akiharu Miyanaga
IPC分类号： H01L29/12 , H01L29/04 , H01L31/036 , H01L31/0376 , H01L31/20 , H01L27/01 , H01L27/12 , H01L21/02 , H01L29/786
CPC分类号： H01L29/7869 , H01L21/02488 , H01L21/02554 , H01L21/02565 , H01L29/04 , H01L29/24 , H01L29/78603
摘要： An object is to provide a semiconductor device including an oxide semiconductor film, which has stable electrical characteristics and high reliability. A stack of first and second material films is formed by forming the first material film (a film having a hexagonal crystal structure) having a thickness of 1 nm to 10 nm over an insulating surface and forming the second material film having a hexagonal crystal structure (a crystalline oxide semiconductor film) using the first material film as a nucleus. As the first material film, a material film having a wurtzite crystal structure (e.g., gallium nitride or aluminum nitride) or a material film having a corundum crystal structure (α-Al2O3, α-Ga2O3, In2O3, Ti2O3, V2O3, Cr2O3, or α-Fe2O3) is used.
摘要翻译：本发明的目的是提供一种具有稳定的电气特性和高可靠性的氧化物半导体膜的半导体装置。通过在绝缘表面上形成厚度为1nm至10nm的第一材料膜（具有六方晶体结构的膜）形成第一和第二材料膜的叠层，并形成具有六方晶系结构的第二材料膜（使用第一材料膜作为核的结晶氧化物半导体膜）。作为第一材料膜，具有纤锌矿晶体结构的材料膜（例如氮化镓或氮化铝）或具有刚玉晶体结构的材料膜（α-Al 2 O 3，α-Ga 2 O 3，In 2 O 3，Ti 2 O 3，V 2 O 3，Cr 2 O 3，或 α-Fe 2 O 3）。

5. 发明申请

US20110315979A1 TRANSISTOR AND SEMICONDUCTOR DEVICE 有权
标题翻译：晶体管和半导体器件
公开(公告)号：US20110315979A1
公开(公告)日：2011-12-29
申请号：US13164296
申请日：2011-06-20
申请人： Masashi Tsubuku , Takayuki Inoue , Suzunosuke Hiraishi , Erumu Kikuchi , Hiromichi Godo , Shuhei Yoshitomi , Koki Inoue , Akiharu Miyanaga , Shunpei Yamazaki
发明人： Masashi Tsubuku , Takayuki Inoue , Suzunosuke Hiraishi , Erumu Kikuchi , Hiromichi Godo , Shuhei Yoshitomi , Koki Inoue , Akiharu Miyanaga , Shunpei Yamazaki
IPC分类号： H01L29/78
CPC分类号： H01L29/7869 , H01L29/408
摘要： Manufactured is a transistor including an oxide semiconductor layer, a source electrode layer and a drain electrode layer overlapping with part of the oxide semiconductor layer, a gate insulating layer overlapping with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode overlapping with part of the oxide semiconductor layer with the gate insulating layer provided therebetween, wherein, after the oxide semiconductor layer which is to be a channel formation region is irradiated with light and the light irradiation is stopped, a relaxation time of carriers in photoresponse characteristics of the oxide semiconductor layer has at least two kinds of modes: τ1 and τ2, τ1
摘要翻译：制造的是包括与氧化物半导体层的一部分重叠的氧化物半导体层，源极电极层和漏极电极层，与氧化物半导体层重叠的栅极绝缘层，源极电极层和漏极电极层的晶体管，以及与所述氧化物半导体层的与氧化物半导体层的一部分重叠的栅电极，其间设置有栅极绝缘层，其中，在作为沟道形成区域的氧化物半导体层被照射光并停止光照射之后，弛豫时间氧化物半导体层的光响应特性中的载流子具有至少两种模式：τ1和τ2，τ1<τ2，τ2为300秒以下。此外，制造包括晶体管的半导体器件。

6. 发明申请

US20110227082A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110227082A1
公开(公告)日：2011-09-22
申请号：US13048023
申请日：2011-03-15
申请人： Takayuki Inoue , Masashi Tsubuku , Suzunosuke Hiraishi , Junichiro Sakata , Erumu Kikuchi , Hiromichi Godo , Akiharu Miyanaga , Shunpei Yamazaki
发明人： Takayuki Inoue , Masashi Tsubuku , Suzunosuke Hiraishi , Junichiro Sakata , Erumu Kikuchi , Hiromichi Godo , Akiharu Miyanaga , Shunpei Yamazaki
IPC分类号： H01L29/786
CPC分类号： H01L29/7869 , H01L27/1225 , H01L29/24 , H01L29/41733 , H01L31/032 , H01L31/18
摘要： An oxide semiconductor layer in which “safe” traps exist exhibits two kinds of modes in photoresponse characteristics. By using the oxide semiconductor layer, a transistor in which light deterioration is suppressed to the minimum and the electric characteristics are stable can be achieved. The oxide semiconductor layer exhibiting two kinds of modes in photoresponse characteristics has a photoelectric current value of 1 pA to 10 nA inclusive. When the average time τ1 until which carriers are captured by the “safe” traps is large enough, there are two kinds of modes in photoresponse characteristics, that is, a region where the current value falls rapidly and a region where the current value falls gradually, in the result of a change in photoelectric current over time.
摘要翻译： “安全”陷阱存在的氧化物半导体层表现出光响应特性的两种模式。通过使用氧化物半导体层，可以实现将光劣化抑制到最小并且电特性稳定的晶体管。在光响应特性中表现出两种模式的氧化物半导体层具有1pA至10nA的光电流值。当通过“安全”陷阱捕获载流子的平均时间τ1足够大时，光响应特性即电流值急剧下降的区域和电流值逐渐下降的区域有两种模式在光电流随时间变化的结果中。

7. 发明授权

US08895976B2 Transistor and semiconductor device 有权
标题翻译：晶体管和半导体器件
公开(公告)号：US08895976B2
公开(公告)日：2014-11-25
申请号：US13164296
申请日：2011-06-20
申请人： Masashi Tsubuku , Takayuki Inoue , Suzunosuke Hiraishi , Erumu Kikuchi , Hiromichi Godo , Shuhei Yoshitomi , Koki Inoue , Akiharu Miyanaga , Shunpei Yamazaki
发明人： Masashi Tsubuku , Takayuki Inoue , Suzunosuke Hiraishi , Erumu Kikuchi , Hiromichi Godo , Shuhei Yoshitomi , Koki Inoue , Akiharu Miyanaga , Shunpei Yamazaki
IPC分类号： H01L29/78 , H01L29/786
CPC分类号： H01L29/7869 , H01L29/408
摘要： Manufactured is a transistor including an oxide semiconductor layer, a source electrode layer and a drain electrode layer overlapping with part of the oxide semiconductor layer, a gate insulating layer overlapping with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode overlapping with part of the oxide semiconductor layer with the gate insulating layer provided therebetween, wherein, after the oxide semiconductor layer which is to be a channel formation region is irradiated with light and the light irradiation is stopped, a relaxation time of carriers in photoresponse characteristics of the oxide semiconductor layer has at least two kinds of modes: τ1 and τ2, τ1
摘要翻译：制造的是包括与氧化物半导体层的一部分重叠的氧化物半导体层，源极电极层和漏极电极层，与氧化物半导体层重叠的栅极绝缘层，源极电极层和漏极电极层的晶体管，以及与所述氧化物半导体层的与氧化物半导体层的一部分重叠的栅电极，其间设置有栅极绝缘层，其中，在作为沟道形成区域的氧化物半导体层被照射光并停止光照射之后，弛豫时间氧化物半导体层的光响应特性中的载流子具有至少两种模式：τ1和τ2，τ1<τ2，τ2为300秒以下。此外，制造包括晶体管的半导体器件。

8. 发明授权

US09799773B2 Transistor and semiconductor device 有权
公开(公告)号：US09799773B2
公开(公告)日：2017-10-24
申请号：US13358556
申请日：2012-01-26
申请人： Hiromichi Godo , Satoshi Kobayashi , Masashi Tsubuku
发明人： Hiromichi Godo , Satoshi Kobayashi , Masashi Tsubuku
IPC分类号： H01L29/78 , H01L29/786 , H01L29/423
CPC分类号： H01L29/7869 , H01L29/42384
摘要： A transistor which withstands a high voltage and controls large electric power can be provided. A transistor is provided which includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer which is over the gate insulating layer and overlaps with the gate electrode, and a source electrode and a drain electrode which are in contact with the oxide semiconductor layer and whose end portions overlap with the gate electrode. The gate insulating layer includes a first region overlapping with the end portion of the drain electrode and a second region adjacent to the first region. The first region has smaller capacitance than the second region.

9. 发明授权

US09437743B2 Thin film element, semiconductor device, and method for manufacturing the same 有权
标题翻译：薄膜元件，半导体器件及其制造方法
公开(公告)号：US09437743B2
公开(公告)日：2016-09-06
申请号：US13237191
申请日：2011-09-20
申请人： Takafumi Mizoguchi , Kojiro Shiraishi , Masashi Tsubuku
发明人： Takafumi Mizoguchi , Kojiro Shiraishi , Masashi Tsubuku
IPC分类号： H01L29/786 , H01L21/764 , H01L27/12
CPC分类号： H01L29/78606 , H01L21/764 , H01L27/1225 , H01L27/1288 , H01L29/24 , H01L29/7869 , H01L29/78696
摘要： An object is to provide a method for manufacturing a semiconductor device without exposing a specific layer to moisture or the like at all. A thin film element is manufactured in such a manner that a first film, a second film, and a third film are stacked in this order; a resist mask is formed over the third film; a mask layer is formed by etching the third film with the use of the resist mask; the resist mask is removed; a second layer and a first layer are formed by performing dry etching on the second film and the first film with the use of the mask layer; a fourth film is formed to cover at least the second layer and the first layer; and sidewall layers are formed to cover at least the entire side surfaces of the first layer by performing etch back on the fourth film.
摘要翻译：本发明的目的是提供一种制造半导体器件的方法，而不会将特定层暴露于湿气等。制造薄膜元件，使得第一膜，第二膜和第三膜按此顺序堆叠; 在第三膜上形成抗蚀剂掩模; 通过使用抗蚀剂掩模蚀刻第三膜来形成掩模层; 去除抗蚀剂掩模; 通过使用掩模层对第二膜和第一膜进行干蚀刻来形成第二层和第一层; 形成第四膜至少覆盖第二层和第一层; 并且通过在第四膜上进行回蚀而形成侧壁层以至少覆盖第一层的整个侧表面。

10. 发明授权

US09082858B2 Transistor including an oxide semiconductor and display device using the same 有权
标题翻译：包括氧化物半导体的晶体管和使用其的显示装置
公开(公告)号：US09082858B2
公开(公告)日：2015-07-14
申请号：US13026511
申请日：2011-02-14
申请人： Masashi Tsubuku , Kosei Noda
发明人： Masashi Tsubuku , Kosei Noda
IPC分类号： H01L29/12 , H01L27/15 , H01L29/786 , H01L27/12
CPC分类号： H01L29/7869 , H01L27/1225 , H01L27/156
摘要： The band tail state and defects in the band gap are reduced as much as possible, whereby optical absorption of energy which is in the vicinity of the band gap or less than or equal to the band gap is reduced. In that case, not by merely optimizing conditions of manufacturing an oxide semiconductor film, but by making an oxide semiconductor to be a substantially intrinsic semiconductor or extremely close to an intrinsic semiconductor, defects on which irradiation light acts are reduced and the effect of light irradiation is reduced essentially. That is, even in the case where light with a wavelength of 350 nm is delivered at 1×1013 photons/cm2·sec, a channel region of a transistor is formed using an oxide semiconductor, in which the absolute value of the amount of the variation in the threshold voltage is less than or equal to 0.65 V.
摘要翻译：频带尾部状态和带隙中的缺陷尽可能地减小，由此减小了在带隙附近或小于或等于带隙的能量的光吸收。在这种情况下，不是仅通过优化氧化物半导体膜的制造条件，而是通过使氧化物半导体成为本质上的本征半导体，或者非常接近本征半导体，减少照射光的作用的缺陷和光照射基本上减少了。也就是说，即使在以1×1013个光子/ cm 2·sec传递波长为350nm的光的情况下，也可以使用氧化物半导体形成晶体管的沟道区域，其中，阈值电压的变化小于或等于0.65 V.

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