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    • 2. 发明授权
    • Thin film transistor and display device
    • 薄膜晶体管和显示装置
    • US08120030B2
    • 2012-02-21
    • US12633067
    • 2009-12-08
    • Hiromichi GodoSatoshi KobayashiHidekazu MiyairiToshiyuki IsaShunpei Yamazaki
    • Hiromichi GodoSatoshi KobayashiHidekazu MiyairiToshiyuki IsaShunpei Yamazaki
    • H01L29/04
    • H01L29/78696H01L27/12H01L29/04
    • Off current of a bottom gate thin film transistor in which a semiconductor layer is shielded from light by a gate electrode is reduced. A thin film transistor includes a gate electrode layer; a first semiconductor layer; a second semiconductor layer, provided on and in contact with the first semiconductor layer; a gate insulating layer between and in contact with the gate electrode layer and the first semiconductor layer; impurity semiconductor layers in contact with the second semiconductor layer; and source and drain electrode layers partially in contact with the impurity semiconductor layers and the first and second semiconductor layers. The entire surface of the first semiconductor layer on the gate electrode layer side is covered by the gate electrode layer; and a potential barrier at a portion where the first semiconductor layer is in contact with the source or drain electrode layer is 0.5 eV or more.
    • 其中半导体层被栅极电极遮挡光的底栅薄膜晶体管的截止电流减小。 薄膜晶体管包括栅电极层; 第一半导体层; 第二半导体层,设置在第一半导体层上并与第一半导体层接触; 在栅极电极层和第一半导体层之间并与之接触的栅极绝缘层; 与第二半导体层接触的杂质半导体层; 以及与杂质半导体层和第一和第二半导体层部分接触的源极和漏极电极层。 栅极电极层侧的第一半导体层的整个表面被栅电极层覆盖; 并且在第一半导体层与源极或漏极电极层接触的部分处的势垒为0.5eV以上。
    • 5. 发明授权
    • Thin film transistor and display device
    • 薄膜晶体管和显示装置
    • US08344380B2
    • 2013-01-01
    • US12633021
    • 2009-12-08
    • Hiromichi GodoSatoshi Kobayashi
    • Hiromichi GodoSatoshi Kobayashi
    • H01L33/00H01L29/786
    • H01L29/78669H01L27/12H01L29/66765H01L29/78609H01L29/78618H01L29/78678H01L29/78696
    • A thin film transistor includes: a gate electrode layer; a first semiconductor layer; a second semiconductor layer having lower carrier mobility than the first semiconductor layer, which is provided over and in contact with the first semiconductor layer; a gate insulating layer which is provided between and in contact with the gate electrode layer and the first semiconductor layer; first impurity semiconductor layers which are provided so as to be in contact with the second semiconductor layer; second impurity semiconductor layers which are provided so as to be partially in contact with the first impurity semiconductor layers and the first and second semiconductor layers; and source and drain electrode layers which are provided so as to be in contact with entire surfaces of the second impurity semiconductor layers, in which an entire surface of the first semiconductor layer on the gate electrode layer side overlaps with the gate electrode layer.
    • 薄膜晶体管包括:栅极电极层; 第一半导体层; 具有比所述第一半导体层低的载流子迁移率的第二半导体层,其设置在所述第一半导体层上并与其接触; 栅极绝缘层,设置在栅电极层和第一半导体层之间并与栅电极层和第一半导体层接触; 设置为与第二半导体层接触的第一杂质半导体层; 第二杂质半导体层,其设置成部分地与第一杂质半导体层以及第一和第二半导体层接触; 以及源极和漏极电极层,其设置成与第二杂质半导体层的整个表面接触,其中栅极电极层侧的第一半导体层的整个表面与栅极电极层重叠。
    • 6. 发明授权
    • Thin film transistor and display device having the thin film transistor
    • 薄膜晶体管和具有薄膜晶体管的显示装置
    • US08253138B2
    • 2012-08-28
    • US12263702
    • 2008-11-03
    • Shunpei YamazakiSatoshi KobayashiYoshiyuki KurokawaHiromichi Godo
    • Shunpei YamazakiSatoshi KobayashiYoshiyuki KurokawaHiromichi Godo
    • H01L29/04
    • H01L29/04H01L21/02532H01L21/0262H01L29/41733H01L29/66765H01L29/78696
    • A thin film transistor includes a gate electrode, a gate insulating layer covering the gate electrode, a microcrystalline semiconductor layer over the gate insulating layer, an amorphous semiconductor layer over the microcrystalline semiconductor layer, source and drain regions over the amorphous semiconductor layer, source and drain electrodes in contact with and over the source and drain regions, and a part of the amorphous semiconductor layer overlapping with the source and drain regions is thicker than a part of the amorphous semiconductor layer overlapping with a channel formation region. The side face of the source and drain regions and the side face of the amorphous semiconductor form a tapered shape together with an outmost surface of the amorphous semiconductor layer. The taper angle of the tapered shape is such an angle that decrease electric field concentration around a junction portion between the source and drain regions and the amorphous semiconductor layer.
    • 薄膜晶体管包括栅电极,覆盖栅电极的栅极绝缘层,栅极绝缘层上的微晶半导体层,微晶半导体层上的非晶半导体层,非晶半导体层上的源极和漏极区,源极和 与源极和漏极区域接触和超过的漏极电极,与源极和漏极区域重叠的部分非晶半导体层比与沟道形成区域重叠的非晶半导体层的一部分更厚。 源极和漏极区域的侧面和非晶半导体的侧面与非晶半导体层的最外表面一起形成锥形形状。 锥形形状的锥角是减小源极和漏极区域与非晶半导体层之间的接合部周围的电场浓度的角度。
    • 8. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08916866B2
    • 2014-12-23
    • US13279868
    • 2011-10-24
    • Hiromichi GodoSatoshi Kobayashi
    • Hiromichi GodoSatoshi Kobayashi
    • H01L29/786H01L21/00
    • H01L29/7869H01L29/78648
    • A semiconductor device includes a first gate electrode; a gate insulating layer covering the first gate electrode; an oxide semiconductor layer that overlaps with the first gate electrode; oxide semiconductor layers having high carrier density covering end portions of the oxide semiconductor layer; a source electrode and a drain electrode in contact with the oxide semiconductor layers having high carrier density; an insulating layer covering the source electrode, the drain electrode, and the oxide semiconductor layer; and a second gate electrode that is in contact with the insulating layer. Each of the oxide semiconductor layers is in contact with part of each of an upper surface, a lower surface, and a side surface of one of the end portions of the oxide semiconductor layer and part of an upper surface of the gate insulating layer.
    • 半导体器件包括第一栅电极; 覆盖所述第一栅电极的栅极绝缘层; 与所述第一栅电极重叠的氧化物半导体层; 具有覆盖氧化物半导体层的端部的高载流子密度的氧化物半导体层; 与具有高载流子密度的氧化物半导体层接触的源电极和漏电极; 覆盖源电极,漏电极和氧化物半导体层的绝缘层; 以及与绝缘层接触的第二栅电极。 每个氧化物半导体层与氧化物半导体层的一个端部和栅极绝缘层的上表面的一部分的上表面,下表面和侧表面的一部分接触。
    • 9. 发明授权
    • Semiconductor device, power diode, and rectifier
    • 半导体器件,功率二极管和整流器
    • US08835917B2
    • 2014-09-16
    • US13220992
    • 2011-08-30
    • Shunpei YamazakiHiromichi GodoSatoshi Kobayashi
    • Shunpei YamazakiHiromichi GodoSatoshi Kobayashi
    • H01L29/10H01L29/786
    • H01L29/7869H01L29/24H01L29/42356H01L29/78648
    • An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.
    • 本发明的目的是提供具有诸如高耐受电压,低反向饱和电流和高导通电流等电特性的半导体器件。 特别地,目的是提供一种包括非线性元件的功率二极管和整流器。 本发明的一个实施例是一种半导体器件,包括第一电极,覆盖第一电极的栅极绝缘层,与栅极绝缘层接触并与第一电极重叠的氧化物半导体层,覆盖端部的一对第二电极 所述氧化物半导体层的绝缘层,覆盖所述一对第二电极和所述氧化物半导体层的绝缘层,以及与所述绝缘层和所述一对第二电极接触的第三电极。 一对第二电极与氧化物半导体层的端面接触。