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1. 发明授权

US07825936B1 Method and system for texture instruction demotion optimization 有权
标题翻译：纹理指令降级优化的方法和系统
公开(公告)号：US07825936B1
公开(公告)日：2010-11-02
申请号：US10993700
申请日：2004-11-19
申请人： Rui M. Bastos , Jakob Nebeker , Emmett M. Kilgariff
发明人： Rui M. Bastos , Jakob Nebeker , Emmett M. Kilgariff
IPC分类号： G09G5/00 , G06T1/00
CPC分类号： G06T1/20
摘要： A method and system for optimizing graphics program execution by allowing the sharing of shader resources is disclosed. The method includes accessing a graphics program using a shader pipeline. If a texture projective instruction is included in the graphics program, a determination is made as to whether a texture projective parameter q indicates a non-projective texture. If the texture projective parameter indicates a non-projective texture, the texture projective instruction is demoted and a resulting demoted texture instruction is executed using a plurality of interpolators of the shader pipeline, which requires fewer shader resources.
摘要翻译：公开了通过允许共享着色器资源来优化图形程序执行的方法和系统。该方法包括使用着色器管线访问图形程序。如果图形程序中包括纹理投影指令，则确定纹理投影参数q是否表示非投影纹理。如果纹理投影参数指示非投影纹理，则纹理投影指令被降级，并且使用着色器流水线的多个内插器执行结果降级的纹理指令，这需要较少的着色器资源。

2. 发明授权

US07624255B1 Scheduling program instruction execution by using fence instructions 有权
标题翻译：使用栅栏指令调度程序指令执行
公开(公告)号：US07624255B1
公开(公告)日：2009-11-24
申请号：US11076201
申请日：2005-03-09
申请人： Christian Rouet , Rui M. Bastos , Emmett M. Kilgariff
发明人： Christian Rouet , Rui M. Bastos , Emmett M. Kilgariff
IPC分类号： G06F9/30
CPC分类号： G06F9/30087 , G06F8/445 , G06F9/3836 , G06F9/3867 , G06F9/3885 , G06T15/005
摘要： A system and method controls the scheduling of program instructions included in a shader program for execution by a processing pipeline. One or more fence instructions may be inserted into the shader program. Each fence instruction specifies a constraint that is applied to control the scheduling of another program instruction in the shader program. Controlling the scheduling of program instructions for execution by the processing pipeline may result in a more efficient use of computing resources and improved performance.
摘要翻译：系统和方法控制包括在着色器程序中的程序指令的调度以供处理管线执行。可以将一个或多个栅栏指令插入到着色器程序中。每个栅栏指令都指定一个约束条件，用于控制着色器程序中另一个程序指令的调度。控制由处理流水线执行的程序指令的调度可以导致计算资源的更有效的使用和改进的性能。

3. 发明授权

US07218291B2 Increased scalability in the fragment shading pipeline 有权
标题翻译：增加片段着色管道中的可扩展性
公开(公告)号：US07218291B2
公开(公告)日：2007-05-15
申请号：US10940070
申请日：2004-09-13
申请人： Karim M. Abdalla , Emmett M. Kilgariff , Rui M. Bastos
发明人： Karim M. Abdalla , Emmett M. Kilgariff , Rui M. Bastos
IPC分类号： G09G1/14 , G06T15/50
CPC分类号： G06T11/40 , G06T15/005 , G06T15/50 , G06T15/80
摘要： A fragment processor includes a fragment shader distributor, a fragment shader collector, and a plurality of fragment shader pipelines. Each fragment shader pipeline executes a fragment shader program on a segment of fragments. The plurality of fragment shader pipelines operate in parallel, executing the same or different fragment shader programs. The fragment shader distributor receives a stream of fragments from a rasterization unit and dispatches a portion of the stream of fragments to a selected fragment shader pipeline until the capacity of the selected fragment shader pipeline is reached. The fragment shader distributor then selects another fragment shader pipeline. The capacity of each of the fragment shader pipelines is limited by several different resources. As the fragment shader distributor dispatches fragments, it tracks the remaining available resources of the selected fragment shader pipeline. A fragment shader collector retrieves processed fragments from the plurality of fragment shader pipelines.
摘要翻译：片段处理器包括片段着色器分配器，片段着色器收集器和多个片段着色器管线。每个片段着色器流水线在片段片段上执行片段着色器程序。多个片段着色器管线并行操作，执行相同或不同的片段着色器程序。片段着色器分配器从光栅化单元接收片段流，并将片段流的一部分分派到所选择的片段着色器管线，直到达到所选片段着色器管线的容量。片段着色器分配器然后选择另一个片段着色器管道。每个片段着色器管道的容量受到几个不同的资源的限制。当片段着色器分配器调度片段时，它会跟踪所选片段着色器管道的剩余可用资源。片段着色器收集器从多个片段着色器管道中检索已处理的片段。

4. 发明授权

US07609272B1 Partial texture loads 有权
标题翻译：局部纹理负载
公开(公告)号：US07609272B1
公开(公告)日：2009-10-27
申请号：US11010972
申请日：2004-12-13
申请人： Emmett M. Kilgariff , Rui M. Bastos
发明人： Emmett M. Kilgariff , Rui M. Bastos
IPC分类号： G06T1/00 , G06T11/40 , G09G5/00
CPC分类号： G06T15/005 , G06T15/04 , G06T15/80 , G09G5/363 , G09G2360/06 , G09G2360/18
摘要： Circuits, methods, and apparatus that provide for partial texture load instructions. Instead of one instruction that may take several shader passes to complete, several instructions are issued, where each instruction is an instruction to retrieve a part or portion of a texture. While each instruction is performed, the other shader circuits can perform other instructions, thus increasing the utilization of the shader circuits when large textures are read from memory. Since several shader passes may be required to read a texture, if a particular instruction needs the texture, one exemplary embodiment reorders instructions such that other instructions are performed before the particular instruction that needs the texture.
摘要翻译：提供部分纹理加载指令的电路，方法和设备。代替一个可能需要几个着色器遍的指令，就会发出几条指令，其中每条指令都是一条用于检索纹理的一部分或部分的指令。当执行每条指令时，其他着色器电路可以执行其他指令，从而在从存储器读取大纹理时增加着色器电路的利用率。由于读取纹理可能需要几个着色器遍，如果特定指令需要纹理，则一个示例性实施例重新排列指令，使得在需要纹理的特定指令之前执行其他指令。

5. 发明授权

US07852340B2 Scalable shader architecture 有权
标题翻译：可扩展着色器架构
公开(公告)号：US07852340B2
公开(公告)日：2010-12-14
申请号：US11957358
申请日：2007-12-14
申请人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J.M. Toksvig , Johnny S Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
发明人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J.M. Toksvig , Johnny S Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
IPC分类号： G06F15/80 , G06T15/50 , G06T15/00
CPC分类号： G06T15/005
摘要： A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
摘要翻译：公开了可扩展着色器架构。根据该架构，着色器包括多个着色器管线，每个着色器管线可以对光栅化像素数据执行处理操作。着色器管线可以根据需要进行功能删除，从而防止着色器流水线造成芯片排斥。着色器包括一个着色器分配器，用于处理光栅化的像素数据，然后有选择地将经处理的光栅化像素数据分配到各种着色器管道，有利于平衡工作负载。着色器收集器将各种着色器管线的输出格式化为正确的顺序，以形成阴影像素数据。着色器指令处理器（调度器）对各个着色器管线进行编程，以执行其预期任务。每个着色器管道具有与着色器分配器和着色器指令处理器交互的着色器网守，使得通过着色器管线的像素数据被根据需要被控制和处理。

6. 发明授权

US07623132B1 Programmable shader having register forwarding for reduced register-file bandwidth consumption 有权
标题翻译：可编程着色器具有寄存器转发功能，可减少寄存器文件带宽消耗
公开(公告)号：US07623132B1
公开(公告)日：2009-11-24
申请号：US11019975
申请日：2004-12-20
申请人： Rui M. Bastos , Christian Rouet , Emmett M. Kilgariff
发明人： Rui M. Bastos , Christian Rouet , Emmett M. Kilgariff
IPC分类号： G06T1/20 , G09G5/36
CPC分类号： G09G5/363 , G06T15/005 , G06T15/80 , G09G5/39
摘要： A method and apparatus of operating a shader having multiple texture or shader processing stations. That method includes feeding the output of a texture or shader processing station directly into the input of another texture or shader processing station. Further, only a subset of the processing stations has access to a shader register file.
摘要翻译：一种操作具有多个纹理或着色器处理站的着色器的方法和装置。该方法包括将纹理或着色器处理站的输出直接馈送到另一个纹理或着色器处理站的输入。此外，只有处理站的子集才能访问着色器寄存器文件。

7. 发明授权

US07486290B1 Graphical shader by using delay 有权
标题翻译：图形着色器使用延迟
公开(公告)号：US07486290B1
公开(公告)日：2009-02-03
申请号：US11149717
申请日：2005-06-10
申请人： Emmett M. Kilgariff , Rui M. Bastos , Wei-Chao Chen , Douglas J. Hahn
发明人： Emmett M. Kilgariff , Rui M. Bastos , Wei-Chao Chen , Douglas J. Hahn
IPC分类号： G06F15/00
CPC分类号： G06T15/005 , G06T2210/52
摘要： A graphical shader and a method of distributing graphical data to shader pipelines in a graphical shader are disclosed. In accordance with the method, a shader pipeline input delay is set. Further, a group of the graphical data is distributed to a shader pipeline of the graphical shader to be processed. The method includes waiting for the shader pipeline input delay to elapse. After the shader pipeline input delay has elapsed, another group of the graphical data is distributed to another shader pipeline of the graphical shader to be processed. In another embodiment, a graphical shader includes a plurality of shader pipelines for processing graphical data. Further, the graphical shader includes a shader distributor for distributing a group of the graphical data to one of the shader pipelines and for distributing another group of the graphical data to another one of the shader pipelines after a shader pipeline input delay has elapsed.
摘要翻译：公开了一种图形着色器和在图形着色器中将图形数据分配到着色器管线的方法。根据该方法，设置着色器管线输入延迟。此外，一组图形数据被分配到要处理的图形着色器的着色器管线。该方法包括等待着色器流水线输入延迟过去。在着色器流水线输入延迟已经过去之后，另一组图形数据被分配到要处理的图形着色器的另一个着色器流水线。在另一个实施例中，图形着色器包括用于处理图形数据的多个着色器管线。此外，图形着色器包括着色器分配器，用于将一组图形数据分配到着色器管道中的一个，并且在着色器流水线输入延迟已经过去之后，将另一组图形数据分配给另一个着色器管线。

8. 发明授权

US07385607B2 Scalable shader architecture 有权
标题翻译：可扩展着色器架构
公开(公告)号：US07385607B2
公开(公告)日：2008-06-10
申请号：US10938042
申请日：2004-09-10
申请人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J. M. Toksvig , Johnny S. Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
发明人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J. M. Toksvig , Johnny S. Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
IPC分类号： G06F15/16 , G06F15/80 , G06T1/20
CPC分类号： G06T15/005
摘要： A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
摘要翻译：公开了可扩展着色器架构。根据该架构，着色器包括多个着色器管线，每个着色器管线可以对光栅化像素数据执行处理操作。着色器管线可以根据需要进行功能删除，从而防止着色器流水线造成芯片排斥。着色器包括一个着色器分配器，用于处理光栅化的像素数据，然后有选择地将经处理的光栅化像素数据分配到各种着色器管道，有利于平衡工作负载。着色器收集器将各种着色器管线的输出格式化为正确的顺序，以形成阴影像素数据。着色器指令处理器（调度器）对各个着色器管线进行编程，以执行其预期任务。每个着色器管道具有与着色器分配器和着色器指令处理器交互的着色器网守，使得通过着色器管线的像素数据被根据需要被控制和处理。

9. 发明授权

US07324113B1 Perspective correction computation optimization 有权
标题翻译：透视校正计算优化
公开(公告)号：US07324113B1
公开(公告)日：2008-01-29
申请号：US11076200
申请日：2005-03-09
申请人： Christian Rouet , Rui M. Bastos , Emmett M. Kilgariff
发明人： Christian Rouet , Rui M. Bastos , Emmett M. Kilgariff
IPC分类号： G06T1/00 , G09G5/00
CPC分类号： G06T15/005 , G09G5/005 , G09G5/363 , G09G5/393
摘要： A method of optimizing perspective correction computations to be executed in a programmable fragment shader, identifying a sequence of program instructions; determining whether the sequence of program instructions can be optimized based on the status of the bit; sourcing one or more interpolated texture map coordinates to thereby disable the perspective correction computation comprising division by (1/w); and enabling the optimized execution of one of a plurality of perspective computation functions by a sought operation in a shader unit without division of the interpolated texture maps coordinates by (1/w). The optimized function includes able mapping, projective mapping, normalization, or scaling invariant operations.
摘要翻译：一种优化在可编程片段着色器中执行的透视校正计算的方法，识别程序指令的序列; 确定是否可以基于位的状态来优化程序指令的序列; 提供一个或多个内插纹理贴图坐标，从而禁止包括除以（1 / w）的透视校正计算; 并且通过在着色器单元中的寻找操作来实现多个透视计算功能中的一个的优化执行，而不使内插纹理映射坐标乘以（1 / w）。优化的功能包括能够映射，投影映射，归一化或缩放不变操作。

10. 发明授权

US07916151B1 Partial texture loads 有权
标题翻译：局部纹理负载
公开(公告)号：US07916151B1
公开(公告)日：2011-03-29
申请号：US12603903
申请日：2009-10-22
申请人： Emmett M. Kilgariff , Rui M. Bastos
发明人： Emmett M. Kilgariff , Rui M. Bastos
IPC分类号： G06T1/00 , G06T11/40 , G09G5/00
CPC分类号： G06T15/005 , G06T15/04 , G06T15/80 , G09G5/363 , G09G2360/06 , G09G2360/18
摘要： Circuits, methods, and apparatus that provide for partial texture load instructions. Instead of one instruction that may take several shader passes to complete, several instructions are issued, where each instruction is an instruction to retrieve a part or portion of a texture. While each instruction is performed, the other shader circuits can perform other instructions, thus increasing the utilization of the shader circuits when large textures are read from memory. Since several shader passes may be required to read a texture, if a particular instruction needs the texture, one exemplary embodiment reorders instructions such that other instructions are performed before the particular instruction that needs the texture.
摘要翻译：提供部分纹理加载指令的电路，方法和设备。代替一个可能需要几个着色器遍的指令，就会发出几条指令，其中每条指令都是一条用于检索纹理的一部分或部分的指令。当执行每条指令时，其他着色器电路可以执行其他指令，从而在从存储器读取大纹理时增加着色器电路的利用率。由于读取纹理可能需要几个着色器遍，如果特定指令需要纹理，则一个示例性实施例重新排列指令，使得在需要纹理的特定指令之前执行其他指令。

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